Early work in this field was based on a minimum-inverter-gain
criterion, and a minimum supply voltage of 200mV was found for
inverters operating in weak inversion [76].
To determine an absolute lower bound of the supply voltage we assume
MOSFETs operating completely in the weak inversion mode.
The drain current is then given by
[A3]
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(2.14) |
Solving (2.12) and (2.13) numerically,
together with (2.4.1) and (2.15) yields noise margins and
maximum gain as a function of the supply voltage.
Fig. 2.4 shows a plot of
and
vs.
.
![]() |
For the design of digital circuits we have to impose certain
constraints, i.e., to specify minimum values for
and
at
a nominal and maximum temperature and to estimate the impact of an
effective unsymmetry
as a consequence of
the fan-in of gates in a
minimum-transistor-size design. This is accounted for by a shift of
the input voltage
.
Minimum supply voltages for various constraints are
compiled in Table 2.2. For static logic with a fan-in of
3 the minimum
is 83mV at 300K or 3.22 times the thermal voltage.
Note that these numbers are absolute lower bounds which cannot likely
be achieved with any CMOS process technology. Achievable values for
may be estimated by scaling the numbers from
Table 2.2 by a factor of
where S
is an achievable average gate swing.
Although this is not consistent with (2.12) and (2.13),
it can be used as a worst-case estimate for subthreshold operation.