A.2.2.1 CMOS Inverters

Fig. A.5 shows the circuit of a CMOS inverter, which illustrates the principle of complementary MOS circuits: when the input voltage is the NMOS switch is on and the PMOS is off. Thus, the output is connected to ground only and the output voltage is 0V. Otherwise, when the input voltage is 0V the PMOS switch is on and the NMOS is off so that the output is connected to the supply rail. The output of the inverter is the complement $\overline{A}$ of its input A. Inverters are used not only for complementing a signal but also for buffering, as line drivers and repeaters, and as amplifiers.

Figure A.5: CMOS inverter

[Circuit]

[Symbol]

[Functional table]

		in	out
	0V	HIGH	LOW
0V		LOW	HIGH

Figure A.6: Definition of the static noise margins

Whether an inverter works properly or not is determined by a set of functional criteria. The first criterion is the inverter gain which must be at least 4 (some authors require a minimum of 10). The second criterion are the so-called noise margins and , i.e. the maximum noise signal which can be superimposed on a digital signal without causing a malfunction of the circuit. Figure A.6 shows the transfer curve of an inverter and the definition of the noise margins. If the output voltage of a stage plus the noise does not drive the following stage beyond the point where $\left\vert\ensuremath{A_{\mathit{inv}}}\xspace \right\vert > 1$ the noise will be attenuated rather than amplified. Thus, the maximum/minimum input and output voltages , , , and are defined by the critical points where $\left\vert\ensuremath{A_{\mathit{inv}}}\xspace \right\vert = 1$. The noise margins are then

$$\renewcommand {1.20}{1.6} \begin{array}{rcl} \ensuremat... ...\xspace }{\ensuremath{V_{\mathit{DD}}}\xspace }} \end{array}$$ (A.18)

The minimum required value for the noise margins is 10% . As this criterion applies also to logic gates the noise margins of simple inverters must be accordingly larger, typically 30% for gates with up to 3 inputs.