As the gate lengths are reduced a variety of technological and electrical problems arise which being tackled by using more sophisticated device structures like the one shown in Fig. A.3 (for a legend of materials see Fig. A.19). The topology is essentially the same as that of the long-channel transistor, but the topography, especially, the dopant profile is modified in order to reduce parasitic resistances and capacitances and to make the depletion zones in the vicinity of the channel smaller. This is achieved by increasing the channel doping, by reducing the depth of the source and drain junctions, and by using source/drain extensions with even shallower junctions at the gate edges (if the source/drain doping were all shallow the parasitic resistance would be too high). To maintain the desired threshold voltage at increased channel doping and to improve the drivability, i.e., the gate oxide thickness is decreased as well. To reduce the sheet resistance of the source/drain areas even further a so-called salicide (self-aligned silicide) with good conductivity is formed by a chemical reaction of a metal (e.g., Ti or Co).