Cracks may be created at any stage of a manufacturing process, but the deposition process step is generally the most problematic. The cracks are observed during the deposition of the passivation layers that cover IC chips in the areas where the top metalization layout geometry yields a three-dimensional profile for the deposition of the passivation layers.
To avoid such cracking and subsequent device failure, it is essential to characterize the deposition profile of the passivation layers as a function of the layout geometry. This characterization can then be used to establish a set of layout design rules to mitigate the formation of crack. An efficient and fast approach is the use of deposition simulation tools. Therefore, having a general purpose topography simulator capable of handling different physical etching and deposition models is essential. We present investigations during deposition of silicon nitride and silicon dioxide to gain insight into possible layout design rules that may be taken into account to avoid crack formation.
As mentioned in Section 6.2.1, the transport of particles is in the radiosity regime [80] for the considered processes. The deposition processes are governed by luminescent reflection. The deposited films are silicon nitride and silicon dioxide films.
Since measurements can only be made from cross sectional SEM images in two dimensions, for three-dimensional deposition simulations we have used the same parameters which were extracted with the optimization and calibration tool SIESTA [35] for two-dimensional simulations. The first set of parameters comes from the simulation results of the deposition of silicon nitride into interconnect lines as shown in [12] and the second set comes from the simulation results of the deposition of silicon dioxide from a TEOS process performed in [9]. These parameters led to very good agreement of simulation results with measurements in two dimensions.
Since our simulations [10] have shown that the metal width does not play an
important role for void characteristics, it will be held constant during all
investigations. The first set of simulations was performed for
different line to line spacings holding the metal thicknesses at
and
. As
mentioned in Section 8.1 the deposited layers were silicon dioxide
and silicon nitride with thicknesses of
and
, respectively.
One of the initial structures considered for
the first set of investigations can be seen in
Figure 8.2. The simulation of the deposition processes into
this structure has led to a result as shown in
Figure 8.3. To analyze the cracking effects we introduce a parameter which is calculated as
follows:
The simulations have generally shown that increasing shifts the void
upwards while it simultaneously decreases
as can be seen by a
comparing Figure 8.3 and Figure 8.4. In addition, increasing
causes the void to be wider. To see the formation of the
void more clearly, a cross section of the simulation result shown in
Figure 8.4 is given in Figure 8.5.
In order to find the influence of the metal thickness on , we have
performed another set of simulations. The dependence of
on different metal thicknesses is
illustrated in Figure 8.6. Whereas the metal
thickness does not considerably affect
for small
, its
effect is stronger once
crossed a threshold value,
and the thicker the metal the larger is
.
So far we have presented three-dimensional simulations with results which could also have been estimated with two-dimensional simulations at the expense of a lower accuracy.
We now present investigations which can only be performed using
three-dimensional
simulations [8]. In a first
attempt is varied while
keeping the remaining parameters constant. Although increasing
shifts
the voids upwards, the dimensions of the voids
do not increase as when increasing
.
Introducing a parameter and its variation results in pronounced
three-dimensional effects. Because
is not a single-valued function of
and
as shown in Figure 8.1, considering the dependence of
on
is difficult. Therefore, it is
very important to have a profile of
depending on
and
that
leads to the same value of
with different combinations of
and
.
Figures 8.7, 8.8, and 8.9 show three of many investigations for different
and
. As in Figure 8.5 we show cross sections of
simulation results shown in Figures 8.7, 8.8, and 8.9, in Figures 8.10, 8.11,
and 8.12, respectively. These figures show that simultaneous increase
of
and
results in three different effects. First, the voids
are shifted upwards. Second, they will be wider. Finally, their height is
decreased. These investigations have led to a profile of
as shown in
Figure 8.13. The important characteristic of
Figure 8.13 is that there are different regions which
guarantee a stable process, i.e., a large
. Using such profiles,
can be predicted
and therefore process engineers will be able to choose
the optimal geometrical parameters to avoid cracks. The cracks are
avoided by choosing
as large as possible because the smaller
the more probable is the formation of cracks.
The void characteristics during the deposition of silicon
dioxide and silicon nitride layers into interconnect lines are
predicted. We have obtained a profile of which determines the
probability of cracking effects. Process engineers can set
layout design rules depending on geometrical parameters while they
choose such parameters leading to larger
because the smaller
the more probable are cracking effects.