Next: 4.2.1 Verification of the Interface State Density Distribution Uniformity Up: 4. The Charge-Pumping Technique Previous: 4.1.2 Effective Channel Length
The density of interface traps along the Si/SiO2 interface of an MOSFET is significantly influenced by the fabrication process and the device geometry. The requirement to consider a number of factors with a variety of physical properties results in the absence of an established model describing initial transistor defect profile at this time. Unfortunately, theoretical calculations of the defect concentration is a very complicated problem and no known solution exists. One of the most widely used experimental methods to obtain this information is the CP technique [173]. In papers devoted to extraction algorithms of the lateral interface state density Nit(x) profile from the CP current, different assumptions regarding the initial interface trap concentration (of a fresh device) have been used. Only a few papers verify the initial profile uniformity [175,177,164]. At the same time, most techniques for the Nit(x) extraction from CP data assume that the initial Nit(x) is homogeneous [178,176]. This assumption is only a simplification, not supported by physical reasoning. The presence of a nonuniform pre-stressed Nit profile is usually ignored while modeling the evolution of Nit(x) during hot-carrier degradation. In fact, HCD-induced Nit may easily reach 1012cm-2, while the initial Nit has typical values of ~1010cm-2. However, the hot-carrier stress is usually performed at voltages higher than operating ones. At operating conditions and/or short stress times, the interface state density is characterized by moderate values, comparable with pre-stressed Nit. Therefore, for a proper description of HCD at operating conditions the information concerning the initial interface state concentration is of significant importance. In this Section an attempt to combine relevant approaches for pre-stressed Nit(x) extraction from CP measurements [173,175,177,164,179] within a single framework (thereby implementing an exhaustive technique) is undertaken. The suggested scheme takes a number of factors affecting the CP current behavior into account.
For analysis of the pre-stressed Nit profile an n-type MOSFET fabricated on a standard 0.35um CMOS process (device architecture and the net doping profile are sketched in Figure 3.2) is used. The constant base-level charge pumping technique [180,176,178] with a fixed base level Vgl = -5V and Vgh increasing from -4V to 4V of the gate pulse has been employed to investigate the interface state density. A device channel width of W = 10um was chosen to obtain a sufficient charge pumping signal. A standard experimental scheme with the gate of the transistor connected to a pulse generator and a small constant reverse bias applied to the source and drain was used. The substrate current (Icp) was monitored. Only the charge pumping current of the unstressed device is considered in this Section.