Abstract

Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided.

Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the ``inner functioning'' of a transistor.

In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth.

Two device generations are considered, one with 0.25 $\mu$m, the other with 0.1 $\mu$m gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes.

In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/$\mu$m. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45% and 71% for the 0.25 $\mu$m and 0.1 $\mu$m devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for its superior drive performance are given. It is compared to already known device structures and practical alternatives are suggested with respect to its manufacturability.

In a second optimization study the gate delay times of complete CMOS inverters are minimized. Both the doping profiles of the NMOS and PMOS transistors are optimized at the same time which results again in PCD devices. The inverter speeds are improved by 54% and 97% for the 0.25 $\mu$m and 0.1 $\mu$m devices, respectively.