The complete simulation of electronic devices shows growing significance due to the increasing miniaturization of the device structures. Physical effects which could be neglected a few years ago determine today's semiconductor technology.
An accurate description of the time evolution of the geometry with topography simulation allows on the one hand a better physical understanding of the applied etching and deposition processes, and on the other hand it provides the necessary geometry information for the following process and device simulation.
Presently three-dimensional topography simulation is limited to a few applications due to considerable problems which occur during the extension of the existing two-dimensional models and algorithms. Many of these problems could not be solved until now. This work discusses important algorithms and investigates possible extensions to three-dimensional simulation.
Starting from some basic morphological operations of image processing a new topography simulation method is developed which allows a robust and efficient simulation of three-dimensional structures. The simulation geometry is considered as a two-valued image and represented by cubic material cells. This material representation allows very complex simulation geometries with holes or regions which are completely disconnected from other regions. Many of the problems of present algorithms such as the formation of erroneous surface loops are inherently avoided.
Furthermore, this work describes the commonly used industrial etching and deposition processes and discusses all important physical and chemical effects to provide the basis for the following model development.
The developed simulation method uses macroscopic process models which consider information about flux distributions and surface reactions of incident particles to calculate etch or deposition rates along the surface. In this work, rate models for common topography processes are developed and algorithms for evaluating the models are presented.
Several simulation results demonstrate the applicability of this method to a wide range of problems. The work shows ion milling results considering the redeposition of etched material and plasma etching of trenches which are used for device isolation or as capacitances in storage technology. Moreover, the step coverage of deposition processes, the patterning and metallization of contact holes, as well as the fabrication process of a stacked capacitor cell for high density storage devices are analyzed.