In smart power devices, discrete power semiconductors are merged with additional functional units to increase the usability of the device. The idea is to fabricate one component that integrates control and diagnostic circuits with power devices. In smart power technologies, this is implemented on a single semiconductor die which is typically accomplished using BCD (Bipolar, CMOS, DMOS), also called BiC-DMOS, technology [46,47,48]. With this integration the complexity of external circuits can be reduced, resulting in cost benefits especially for standard high volume components.
In many application fields the advances of smart power devices help to make products cheaper, smaller, and more reliable. Simple transistors are exchanged by smart switching devices or even complete amplifiers. The integrated control and analysis functionality may also allow a direct connection to microprocessors. The higher level of integration reduces the number of components required to design circuits which reduces design and fabrication costs and increases the reliability. Integrated features like load, supply voltage, and temperature monitoring are easily accessible to product designers. It is also possible to fabricate complete microcomputer environments including memory and serial interfaces together with high-voltage and power devices. A wide variety of system on a chip (SoC) solutions can be realized [5].
There are two major approaches for designing smart power devices. One approach is to build the low-voltage part on top of a power device technology [49]. This approach is especially used for high current applications based on vertical device structures (see Fig. 2.10).
![\includegraphics[width=\textwidth]{figures/smart_vertical}](img76.png)
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The other approach is based on a CMOS VLSI (Very Large Scale Integration) process. Here, the CMOS process is extended to allow for the integration of lateral high-voltage and current devices (see Fig. 2.11) [51,5]. Due to high investments made into the field of VLSI by the computer industry, this approach benefits from highly advanced fabrication and design methods. Circuits for smart power devices usually do not require the most advanced VLSI technology node, so the designs can be based on mature, well established process technologies.
Isolation between different devices in integrated circuits plays a key role in integrated device design. A special challenge in smart power devices is the protection of the low-voltage circuits from high voltages. There are basically three different isolation methods in use [6]:
The self isolation technique can be applied when single devices inherently form reverse-biased junctions. CMOS structures (refer Fig. 2.5) are a good example which allow to apply this self isolation technique. Processing of this isolation type is very simple since no special steps have to be introduced. A disadvantage of this technique is the high number of parasitic devices generated due to the missing isolation. Also the flexibility of the circuit is reduced since it has to be assured that the pn-junctions between the devices need to be permanently reverse-biased.
In the junction isolation technique, additional doped areas are introduced between devices to ensure proper isolation. For p-type substrates with n-type epitaxial layers, for example, diffused p-doped regions from the surface down to the substrate are used [6]. An example is shown in Fig. 2.11. This technique is still cost efficient and is often used since it gives higher flexibility than the self isolation technique.
![\includegraphics[width=\textwidth]{figures/smart_horizontal}](img77.png)
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From the isolation point of view, the best option is the dielectric isolation. Here, a silicon dioxide layer separates the devices leading to much lower ohmic and capacitive coupling compared to junction isolation techniques. There are no parasitic devices between the transistors, since there are no additional pn-junctions. Fig. 2.12 shows a typical fabrication method that uses SOI (Silicon On Insulator).
![\includegraphics[width=\textwidth]{figures/smart_horizontal_soi}](img78.png)
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Comparing Fig. 2.11 and 2.12 shows that the isolation structures in SOI require less space and a more compact implementation is possible [49]. Another benefit of the dielectric isolation is that devices next to each other can be operated using arbitrary potentials and it is not required to take care of blocking voltages for the isolating pn-junctions. This makes, for example, the implementation of bridge circuits for stepper motors much easier. However, there are two major disadvantages of the SOI technique. First, the costs of the SOI wafers are still higher compared to standard wafers [52]. However, the reduction of the required surface often compensates these additional costs [53]. The second problem is the low thermal conductivity of the isolating oxide structures [54,55]. In bulk technology the heat generated in the devices is transported into the bulk of the device very efficiently which is not possible in SOI devices.
Monolithic integration of devices with different power and voltage levels allows to fabricate products for many different applications. A random exemplary selection of devices from industry is given in the following to show some products that are available on the market:
As a first example, the PROFET
(Automotive device series from
Infineon Technologies) high side switch series is probably the most
typical smart power device in this selection. Here, a MOSFET transistor is
enhanced by diagnostic functionality including overload protection, over- and
under-voltage shutdown and auto-restart, current limitation, short circuit
protection, thermal shutdown, and many more features. The main application area
for this device series is the automotive industry. The breakdown voltage range
lies between 28 and 60V. Device failure or load irregularities can therefore
be detected. Hence, the on-board electronic system gets feedback on failure
events, which helps to diagnose or solve the fault.
Two other examples, which are usually not explicitly considered as smart power devices, but nevertheless make extensive use of integration of different technologies. Both are highly integrated applications for single chip solutions, one for mobile phones and the other for mobile audio players. The example of the mobile phone system is from NXP Semiconductors. It includes all required GSM/GPRS applications which are ``[..] the analog and digital basebands, RF transceiver, power management, battery interface and charging electric circuit, and audio in a single monolithic CMOS IC[..]'' (Product description of the PNX4901 from NXP Semiconductors). The other example is for mobile entertainment equipments, like digital music players from ams. It is a system on a chip solution ``[..]for high performance and ultra low power audio products with minimum count of external components[..]'' (Product description of the AS3531 from ams). This component integrates all functionalities required to build a mobile player, including main processor, audio amplifier, display controller, internal memory, external memory interface, battery controller, high-speed serial interface, and many more features.
These examples highlight the high usability that can be achieved by integrating different technologies on the same semiconductor die. The overall system also benefits from the increased reliability using highly integrated chips. One aspect for this is the reduced number of external connections between the single components which makes the printed circuit board smaller and its fabrication more simple. The electric circuit for the specific functionality is shifted into the semiconductor chip which allows an optimized, well tuned design. Additionally electrostatic discharge (ESD) and other hazard impacts can only occur at external terminals, the chip internal connections are not affected.
substrate (simplified from [