Bibliography

1

A. Allan, D. Edenfeld, W. Joyner, A. B. Kahng, M. Rodgers, and Y. Zorian, ``2001 technology roadmap for semiconductors,'' IEEE Computer, vol. 35, no. 1, pp. 42-53, 2002.

2

C. A. Mack, ``Fifty years of Moore's law,'' IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 2, pp. 202-207, 2011.

3

B. J. Baliga, ``Smart power technology: An elephantine opportunity,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 3-6, 1990.

4

B. J. Baliga, ``An overview of smart power technology,'' IEEE Transactions on Electron Devices, vol. 38, no. 7, pp. 1568-1575, 1991.

5

M. Schrems, M. Knaipp, H. Enichlmair, V. Vescoli, R. Minixhofer, E. Seebacher, F. Leisenberger, E. Wachmann, G. Schatzberger, and H. Gensinger, ``Scalable high voltage CMOS technology for smart power and sensor applications,'' Elektrotechnik und Informationstechnik, vol. 125, pp. 109-117, April 2008.

6

A. Andreini, C. Contiero, and P. Galbiati, ``BCD technology for smart power ICs,'' in Smart Power ICs (B. Murari, F. Bertotti, and G. Vignola, eds.), ch. 1, pp. 1-52, Springer, 1996.

7

The Authoritative Dictionary of IEEE Standards Terms - IEEE 100, $7^{th}$ Edition.
IEEE Press, 2000.

8

S. Pendharkar, ``Technology requirements for automotive electronics,'' in Proceedings IEEE Conference Vehicle Power and Propulsion, pp. 834-839, 2005.

9

J.-M. Park, H. Enichlmair, and R. Minixhofer, ``Hot-carrier behaviour of a 0.35 $\mu$ m high-voltage n-channel LDMOS transistor,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 369-372, 2007.

10

H. Casier, P. Moens, and K. Appeltans, ``Technology considerations for automotive,'' in Proceedings European Solid-State Device Research Conference (ESSDERC), pp. 37-41, 2004.

11

S. Selberherr, Analysis and Simulation of Semiconductor Devices.
Springer-Verlag Wien New York, 1984.

12

K. Kramer, G. Nicholas, and W. Hitchon, Semiconductor Devices, a Simulation Approach.
Prentice Hall Professional Technical Reference, 1997.

13

W. Fichtner, K. Esmark, and W. Stadler, ``TCAD software for ESD on-chip protection design,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 14.1.1-14.1.4, 2001.

14

W. Fichtner, N. Braga, M. Ciappa, V. Mickevicius, and M. Schenkel, ``Progress in technology CAD for power devices, circuits and systems,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 1-9, 2005.

15

T. Grasser, T.-W. Tang, H. Kosina, and S. Selberherr, ``A review of hydrodynamic and energy-transport models for semiconductor device simulation,'' Proceedings of the IEEE, vol. 91, no. 2, pp. 251-274, 2003.

16

C. Jungemann and B. Meinerzhagen, Hierarchical Device Simulation: The Monte-Carlo Perspective.
Springer, 2003.

17

S. Tyaginov, I. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.-M. Park, H. Enichlmair, M. Karner, C. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, and T. Grasser, ``Hot-carrier degradation modeling using full-band Monte-Carlo simulations,'' in Proceedings IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 1-5, 2010.

18

S. Tyaginov, I. Starkov, O. Triebl, H. Ceric, T. Grasser, H. Enichlmair, J.-M. Park, and C. Jungemann, ``Secondary generated holes as a crucial component for modeling of HC degradation in high-voltage n-MOSFET,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 123-126, 2011.

19

B. J. Baliga, ``The future of power semiconductor device technology,'' Proceedings of the IEEE, vol. 89, no. 6, pp. 822-832, 2001.

20

J. G. Bauer, T. Duetemeyer, E. Falck, C. Schaeffer, G. Schmidt, and H. Schulze, ``Investigations on 6.5kV trench IGBT and adapted EmCon diode,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 5-8, 2007.

21

M. Vellvehi, D. Flores, X. Jorda, S. Hidalgo, J. Rebollo, L. Coulbeck, and P. Waind, ``Design considerations for 6.5 kV IGBT devices,'' Microelectronics Journal, vol. 35, no. 3, pp. 269-275, 2004.

22

T. Fujii, K. Yoshikawa, T. Koga, A. Nishiura, Y. Takahashi, H. Kakiki, M. Ichijyou, and Y. Seki, ``4.5 kV-2000 A power pack IGBT (ultra high power flat-packaged PT type RC-IGBT),'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 33-36, 2000.

23

C. Kleint, ``Julius Edgar Lilienfeld: Life and profession,'' Progress in Surface Science, vol. 57, pp. 253-327, April 1998.

24

E. J. Lilienfeld, ``Method and apparatus for controlling electric currents,'' Jan 1930, U.S. Patent 1745175.

25

E. J. Lilienfeld, ``Device for controlling electric current,'' March 1933, U.S. Patent 1900018.

26

M. M. Atalla, E. Tannenbaum, and E. J. Scheibner, ``Stabilization of silicon surfaces by thermally grown oxides,'' Bell System Technical Journal, vol. 38, pp. 749-783, 1959.

27

R. G. Arns, ``The other transistor: early history of the metal-oxide semiconductor field-effect transistor,'' Engineering Science and Education Journal, vol. 7, no. 5, pp. 233-240, 1998.

28

B. J. Baliga, ``Trends in power semiconductor devices,'' IEEE Transactions on Electron Devices, vol. 43, no. 10, pp. 1717-1731, 1996.

29

B. J. Baliga, Power Semiconductor Devices.
PWS Publishing Company, 1995.

30

B. J. Baliga, M. S. Adler, R. P. Love, P. V. Gray, and N. D. Zommer, ``The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device,'' IEEE Transactions on Electron Devices, vol. 31, no. 6, pp. 821-828, 1984.

31

T. R. Efland, C.-Y. Tsai, and S. Pendharkar, ``Lateral thinking about power devices (LDMOS),'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 679-682, 1998.

32

S. Sze, Physics of Semiconductor Devices.
New York: Wiley, second ed., 1981.

33

J. Appels and H. Vaes, ``High voltage thin layer devices (RESURF devices),'' in Technical Digest International Electron Devices Meeting (IEDM), vol. 25, pp. 238 - 241, 1979.

34

P. Moens and G. Van den bosch, ``Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS,'' Microelectronics Reliability, vol. 48, no. 8-9, pp. 1300-1305, 2008.

35

M. Amato and V. Rumennik, ``Comparison of lateral and vertical DMOS specific on-resistance,'' in Technical Digest International Electron Devices Meeting (IEDM), vol. 31, pp. 736-739, 1985.

36

M. Knaipp, G. Rohrer, R. Minixhofer, and E. Seebacher, ``Investigations on the high current behavior of lateral diffused high-voltage transistors,'' IEEE Transactions on Electron Devices, vol. 51, no. 10, pp. 1711-1720, 2004.

37

P. Moens, S. Bychikhin, K. Reynders, D. Pogany, E. Gornik, and M. Tack, ``Dynamics of integrated vertical DMOS transistors under 100-ns TLP stress,'' IEEE Transactions on Electron Devices, vol. 52, no. 5, pp. 1008-1013, 2005.

38

A. S. Grove, O. Leistiko, Jr., and W. W. Hooper, ``Effect of surface fields on the breakdown voltage of planar silicon p-n junctions,'' IEEE Transactions on Electron Devices, vol. 14, no. 3, pp. 157-162, 1967.

39

D. Scharfetter and H. Gummel, ``Large-signal analysis of a silicon read diode oscillator,'' IEEE Transactions on Electron Devices, vol. 16, no. 1, pp. 64-77, 1969.

40

A. W. Ludikhuize, ``A review of RESURF technology,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 11-18, 2000.

41

Z. Hossain, T. Ishigwo, L. Tu, H. Corleto, F. Kuramae, and R. Nair, ``Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 237-240, 2004.

42

J. Roig, D. Flores, J. Urresti, S. Hidalgo, and J. Rebollo, ``Modeling of non-uniform heat generation in LDMOS transistors,'' Solid-State Electronics, vol. 49, no. 1, pp. 77-84, 2005.

43

S. Gao, J. Chen, D. Ke, and L. Liu, ``Analytical model for surface electrical field of double RESURF LDMOS with field plate,'' in Proceedings Solid-State and Integrated Circuit Technology (ICSICT), pp. 1324-1326, 2006.

44

P. M. Shenoy, A. Bhalla, and G. M. Dolny, ``Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 99-102, 1999.

45

L. Lorenz, G. Deboy, A. Knapp, and M. Marz, ``COOLMOS $^\mathrm{TM}$ - a new milestone in high voltage power MOS,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 3-10, 1999.

46

A. Andreini, C. Contiero, and P. Galbiati, ``A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts,'' IEEE Transactions on Electron Devices, vol. 33, no. 12, pp. 2025-2030, 1986.

47

W. Horn and H. Zitta, ``A robust smart power bandgap reference circuit for use in an automotive environment,'' IEEE Journal of Solid-State Circuits, vol. 37, no. 7, pp. 949-952, 2002.

48

T. Efland, J. Devore, A. Hastings, S. Pendharkar, and R. Teggatz, ``Bipolar issues in advanced power BiCMOS technology,'' in Proceedings Bipolar/BiCMOS Circuits and Technology Meeting, pp. 20-27, 2000.

49

S. Mukherjee, ``Technologies for high voltage ICs,'' in Smart Power ICs (K. Itoh, T. Lee, T. Sakurai, and D. Schmitt-Landsiedel, eds.), ch. 2, pp. 53-78, Springer, 1996.

50

S. L. Wong, S. Venkitasubrahmanian, M. J. Kim, and J. C. Young, ``Design of a 60-V 10-A intelligent power switch using standard cells,'' IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 429-432, 1992.

51

A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, ``LDMOS implementation in a 0.35 $\mu$ m BCD technology (BCD6),'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 323-326, 2000.

52

T. Trajkovic, N. Udugampola, V. Pathirana, A. Mihaila, F. Udrea, G. A. J. Amaratunga, B. Koutny, K. Ramkumar, and S. Geha, ``High frequency 700V PowerBrane LIGBTs in 0.35 $\mu$ m bulk CMOS technology,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 307-310, 2009.

53

F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakaharna, H. Aoki, and K. Hamada, ``Multi-voltage SOI-BiCDMOS for 14V&42V automotive applications,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 165-168, 2004.

54

Y.-K. Leung, Y. Suzuki, K. E. Goodson, and S. S. Wong, ``Self-heating effect in lateral DMOS on SOI,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 136-140, 1995.

55

H. Lim, F. Udrea, D. Garner, and W. Milne, ``Modelling of self-heating effect in thin SOI and partial SOI LDMOS power devices,'' Solid-State Electronics, vol. 43, no. 7, pp. 1267-1280, 1999.

56

W. Denson, ``The history of reliability prediction,'' IEEE Transactions on Reliability, vol. 47, no. 3, pp. SP321-SP328, 1998.

57

A. Goel and R. Graves, ``Electronic systems reliability: Collating prediction models,'' IEEE Transactions on Device and Materials Reliability, vol. 6, no. 2, pp. 258-265, 2006.

58

I. Snook, J. Marshall, and R. Newman, ``Physics of failure as an integrated part of design for reliability,'' in Proceedings Annual Reliability and Maintainability Symposium, pp. 46-54, 2003.

59

Reliability Prediction of Electronic Equipment (MIL-HDBK-217F Notice 2).
Military Handbook, U.S. Department of Defense, 1995.

60

M. Pecht and F. Nash, ``Predicting the reliability of electronic equipment,'' Proceedings of the IEEE, vol. 82, no. 7, pp. 992-1004, 1994.

61

M. Cushing, D. Mortin, T. Stadterman, and A. Malhotra, ``Comparison of electronics-reliability assessment approaches,'' IEEE Transactions on Reliability, vol. 42, no. 4, pp. 542-546, 1993.

62

S. Morris and J. Reilly, ``MIL-HDBK-217 - A favorite target,'' in Proceedings Annual Reliability and Maintainability Symposium, pp. 503-509, 1993.

63

M. Ohring, Reliability and Failure of Electronic Materials and Devices.
Academic Press, 1998.

64

H. H. Huston and C. P. Clarke, ``Reliability defect detection and screening during processing-theory and implementation,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 268-275, 1992.

65

K. L. Wong, ``The bathtub does not hold water any more,'' Quality and Reliability Engineering International, vol. 4, no. 3, pp. 279-282, 1988.

66

K. L. Wong, ``The roller-coaster curve is in,'' Quality and Reliability Engineering International, vol. 5, no. 1, pp. 29-36, 1989.

67

K. L. Wong, ``The physical basis for the roller-coaster hazard rate curve for electronics,'' Quality and Reliability Engineering International, vol. 7, no. 6, pp. 189-495, 1991.

68

W. Kuo and M. J. Zuo, Optimal Reliability Modeling - Principles and Applications.
Wiley, 2003.

69

M. Bebbington and C.-D. Lai, ``Lifetime analysis of incandescent lamps: The Menon-Agrawal model revisited,'' Reliability & Risk Analysis: Theory & Applications, vol. 1, no. 1, pp. 97-108, 2008.

70

R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E. Maes, ``New insights in the relation between electron trap generation and the statistical properties of oxide breakdown,'' IEEE Transactions on Electron Devices, vol. 45, no. 4, pp. 904-911, 1998.

71

M. Pecht, ``A model for moisture induced corrosion failures in microelectronic packages,'' IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 13, no. 2, pp. 383-389, 1990.

72

C. Chauvet and C. Laurent, ``Weibull statistics in short-term dielectric breakdown of thin polyethylene films,'' IEEE Transactions on Electrical Insulation, vol. 28, no. 1, pp. 18-29, 1993.

73

R. Hill and E. Okoroafor, ``Weibull statistics of fibre bundle failure using mechanical and acoustic emission testing: the influence of interfibre friction,'' Composites, vol. 26, no. 10, pp. 699-705, 1995.

74

W. Kuo, W.-T. K. Chien, and T. Kim, Reliability, Yield, and Stress Burn-In.
Springer US, 1998.

75

K. O. Kim, W. Kuo, and W. Luo, ``A relation model of gate oxide yield and reliability,'' Microelectronics Reliability, vol. 44, no. 3, pp. 425-434, 2004.

76

T. Kim and W. Kuo, ``Modeling manufacturing yield and reliability,'' IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 4, pp. 485-492, 1999.

77

J. C. Lee, C. Ih-Chin, and H. Chenming, ``Modeling and characterization of gate oxide reliability,'' IEEE Transactions on Electron Devices, vol. 35, no. 12, pp. 2268-2278, 1988.

78

F. Kuper, J. van der Pol, E. Ooms, T. Johnson, R. Wijburg, W. Koster, and D. Johnston, ``Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate reduction programs,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 17-21, 1996.

79

A. Buerke, H. Wendrock, and K. Wetzig, ``Study of electromigration damage in Al interconnect lines inside a SEM,'' Crystal Research and Technology, vol. 35, no. 6-7, pp. 721-730, 2000.

80

J. R. Black, ``Electromigration-a brief survey and some recent results,'' IEEE Transactions on Electron Devices, vol. 16, no. 4, pp. 338-347, 1969.

81

M. L. Green, E. P. Gusev, R. Degraeve, and E. L. Garfunkel, ``Ultrathin ($<4$ nm) SiO$_2$ and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits,'' Journal of Applied Physics, vol. 90, no. 5, pp. 2057-2121, 2001.

82

E. Harari, ``Conduction and trapping of electrons in highly stressed ultrathin films of thermal SiO$_2$ ,'' Applied Physics Letters, vol. 30, no. 11, pp. 601-603, 1977.

83

S. Lombardo, J. H. Stathis, B. P. Linder, K. L. Pey, F. Palumbo, and C. H. Tung, ``Dielectric breakdown mechanisms in gate oxides,'' Journal of Applied Physics, vol. 98, no. 12, pp. 121301-1-36, 2005.

84

J. S. Suehle, ``Ultrathin gate oxide reliability: Physical models, statistics, and characterization,'' IEEE Transactions on Electron Devices, vol. 49, no. 6, pp. 958-971, 2002.

85

D. A. Buchanan, J. H. Stathis, E. Cartier, and D. J. DiMaria, ``On the relationship between stress induced leakage currents and catastrophic breakdown in ultra-thin SiO$_2$ based dielectrics,'' Microelectronic Engineering, vol. 36, no. 1-4, pp. 329-332, 1997.

86

L. Pantisano and K. Cheung, ``Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?,'' IEEE Transactions on Device and Materials Reliability, vol. 1, no. 2, pp. 109-112, 2001.

87

D. J. DiMaria, D. A. Buchanan, J. H. Stathis, and R. E. Stahlbush, ``Interface states induced by the presence of trapped holes near the silicon–silicon-dioxide interface,'' Journal of Applied Physics, vol. 77, no. 5, pp. 2032-2040, 1995.

88

D. J. DiMaria, E. Cartier, and D. Arnold, ``Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon,'' Journal of Applied Physics, vol. 73, no. 7, pp. 3367-3348, 1993.

89

I. C. Chen, S. Holland, K. K. Young, C. Chang, and C. Hu, ``Substrate hole current and oxide breakdown,'' Applied Physics Letters, vol. 49, no. 11, pp. 669-671, 1986.

90

K. F. Schuegraf and C. Hu, ``Metal-oxide-semiconductor field-effect-transistor substrate current during Fowler-Nordheim tunneling stress and silicon dioxide reliability,'' Journal of Applied Physics, vol. 76, no. 6, pp. 3695-3700, 1994.

91

R. Degraeve, B. Kaczer, and G. Groeseneken, ``Degradation and breakdown in thin oxide layers: mechanisms, models and reliability prediction,'' Microelectronics Reliability, vol. 39, no. 10, pp. 1445-1460, 1999.

92

J. W. McPherson and H. C. Mogul, ``Underlying physics of the thermochemical E model in describing low-field time-dependent dielectric breakdown in SiO$_2$ thin films,'' Journal of Applied Physics, vol. 84, no. 3, pp. 1513-1523, 1998.

93

J. H. Stathis, ``Percolation models for gate oxide breakdown,'' Journal of Applied Physics, vol. 86, no. 10, pp. 5757-5766, 1999.

94

B. E. Weir, P. J. Silverman, D. Monroe, K. S. Krisch, M. A. Alam, G. B. Alers, T. W. Sorsch, G. L. Timp, F. Baumann, C. T. Liu, Y. Ma, and D. Hwang, ``Ultra-thin gate dielectrics: they break down, but do they fail?,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 73-76, 1997.

95

R. Degraeve, B. Kaczer, and G. Groeseneken, ``Reliability: a possible showstopper for oxide thickness scaling?,'' Semiconductor Science and Technology, vol. 15, pp. 434-444, 2000.

96

T. Grasser and B. Kaczer, ``Negative bias temperature instability: Recoverable versus permanent degradation,'' in Proceedings European Solid-State Device Research Conference (ESSDERC), pp. 127-130, 2007.

97

M. Alam and S. Mahapatra, ``A comprehensive model of pMOS NBTI degradation,'' Microelectronics Reliability, vol. 45, no. 1, pp. 71-81, 2005.

98

R. Entner, T. Grasser, O. Triebl, H. Enichlmair, and R. Minixhofer, ``Negative bias temperature instability modeling for high-voltage oxides at different stress temperatures,'' Microelectronics Reliability, vol. 47, no. 4-5, pp. 697-699, 2007.

99

T. Grasser, W. Gös, and B. Kaczer, ``Dispersive transport and negative bias temperature instability: Boundary conditions, initial conditions, and transport models,'' IEEE Transactions on Device and Materials Reliability, vol. 8, no. 1, pp. 79-97, 2008.

100

T. Grasser, P. Wagner, P. Hehenberger, W. Gös, and B. Kaczer, ``A rigorous study of measurement techniques for negative bias temperature instability,'' IEEE Transactions on Device and Materials Reliability, vol. 8, no. 3, pp. 526-535, 2008.

101

T. Grasser, B. Kaczer, W. Gös, T. Aichinger, P. Hehenberger, and M. Nelhiebel, ``A two-stage model for negative bias temperature instability,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), 2009.

102

T. Grasser, B. Kaczer, W. Gös, T. Aichinger, P. Hehenberger, and M. Nelhiebel, ``Understanding negative bias temperature instability in the context of hole trapping,'' Microelectronic Engineering, vol. 86, no. 7-9, pp. 1876-1882, 2009.

103

K. Kawamoto and S. Takahashi, ``An advanced no-snapback LDMOSFET with optimized breakdown characteristics of drain n-n$^+$ diodes,'' IEEE Transactions on Electron Devices, vol. 51, no. 9, pp. 1432-1440, 2004.

104

D. Kontos, K. Domanski, R. Gauthier, K. Chatty, M. Muhammad, C. Seguin, R. Halbach, C. Russ, and D. Alvarez, ``Investigation of external latchup robustness of dual and triple well designs in 65nm bulk CMOS technology,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 145-150, 2006.

105

D. Lin, ``ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown,'' Journal of Electrostatics, vol. 33, no. 3, pp. 251-271, 1994.

106

S. Voldman, ``A review of electrostatic discharge (ESD) in advanced semiconductor technology,'' Microelectronics Reliability, vol. 44, pp. 33-46, 2004.

107

A. A. Salman, R. Gauthier, C. Putnam, P. Riess, M. Muhammad, M. Woo, and D. E. Ioannou, ``ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-$\mu$ m CMOS technology,'' IEEE Transactions on Device and Materials Reliability, vol. 3, no. 3, pp. 79-84, 2003.

108

J. E. Vinson and J. J. Liou, ``Electrostatic discharge in semiconductor devices: protection techniques,'' Proceedings of the IEEE, vol. 88, no. 12, pp. 1878-1902, 2000.

109

V. De Heyn, G. Groeseneken, B. Keppens, M. Natarajan, L. Vacaresse, and G. Gallopyn, ``Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 253-258, 2001.

110

X. Gao, J. J. Liou, J. Bernier, G. Crof, W. Wong, and S. Vishwanathan, ``Optimization of on-chip ESD protection structures for minimal parasitic capacitance,'' Microelectronics Reliability, vol. 43, no. 5, pp. 725-733, 2003.

111

J. A. Salcedo, J. J. Liou, Z. Liu, and J. E. Vinson, ``TCAD methodology for design of SCR devices for electrostatic discharge (ESD) applications,'' IEEE Transactions on Electron Devices, vol. 54, no. 4, pp. 822-832, 2007.

112

D. Flandre, ``Silicon-on-insulator technology for high temperature metal oxide semiconductor devices and circuits,'' Materials Science and Engineering: B, vol. 29, no. 1-3, pp. 7-12, 1995.

113

R. W. Johnson, J. L. Evans, P. Jacobsen, J. R. Thompson, and M. Christopher, ``The changing automotive environment: high-temperature electronics,'' IEEE Transactions on Electronics Packaging Manufacturing, vol. 27, no. 3, pp. 164-176, 2004.

114

W. Wondrak, ``Physical limits and lifetime limitations of semiconductor devices at high temperatures,'' Microelectronics Reliability, vol. 39, no. 6-7, pp. 1113-1120, 1999.

115

S. Reggiani, M. Valdinoci, L. Colalongo, M. Rudan, G. Baccarani, A. Stricker, F. Illien, N. Felber, W. Fichtner, and L. Zullino, ``Electron and hole mobility in silicon at large operating temperatures. Part I: Bulk mobility,'' IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 490-499, 2002.

116

S. Reggiani, E. Gnani, M. Rudan, G. Baccarani, C. Corvasce, D. Barlini, M. Ciappa, W. Fichtner, M. Denison, N. Jensen, G. Groos, and M. Stecher, ``Experimental extraction of the electron impact-ionization coefficient at large operating temperatures,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 407-410, 2004.

117

D. J. Frank, ``Power-constrained CMOS scaling limits,'' IBM Journal of Research and Development, vol. 46, no. 2, pp. 235-244, 2002.

118

A. Bar-Cohen and M. Iyengar, ``Design and optimization of air-cooled heat sinks for sustainable development,'' IEEE Transactions on Components and Packaging Technologies, vol. 25, no. 4, pp. 584-591, 2002.

119

Y. Li and C. Wong, ``Recent advances of conductive adhesives as a lead-free alternative in electronic packaging: Materials, processing, reliability and applications,'' Materials Science and Engineering: R: Reports, vol. 51, no. 1-3, pp. 1-35, 2006.

120

I$\mu$ E, MINIMOS-NT 2.1 User's Guide.
Institut für Mikroelektronik, Technische Universität Wien, Austria, 2004.

121

Global TCAD Solutions, GTS Framework.
http://www.globaltcad.com.

122

C. Jacoboni and L. Reggiani, ``The Monte Carlo method for the solution of charge transport in semiconductors with application to covalent materials,'' Reviews of Modern Physics, vol. 55, no. 3, pp. 645-705, 1983.

123

M. Lundstrom, Fundamentals of Carrier Transport.
Cambridge University Press, 2000.

124

G. A. Baraff, ``Maximum anisotropy approximation for calculating electron distributions; application to high field transport in semiconductors,'' Physical Review, vol. 133, no. 1A, pp. A26-A33, 1964.

125

C. Jungemann, A. T. Pham, B. Meinerzhagen, C. Ringhofer, and M. Bollhofer, ``Stable discretization of the Boltzmann equation based on spherical harmonics, box integration, and a maximum entropy dissipation principle,'' Journal of Applied Physics, vol. 100, no. 2, pp. 024502-1-13, 2006.

126

M. Vecchi and M. Rudan, ``Modeling electron and hole transport with full-band structure effects by means of the spherical-harmonics expansion of the BTE,'' IEEE Transactions on Electron Devices, vol. 45, no. 1, pp. 230-238, 1998.

127

G. Wachutka, ``Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 11, pp. 1141-1149, 1990.

128

R. Stratton, ``Semiconductor current-flow equations (diffusion and degeneracy),'' IEEE Transactions on Electron Devices, vol. 19, no. 12, pp. 1288-1292, 1972.

129

W. VanRoosbroeck, ``Theory of flow of electrons and holes in germanium and other semiconductors,'' Bell System Technical Journal, vol. 29, pp. 560-607, 1950.

130

T. Grasser, H. Kosina, M. Gritsch, and S. Selberherr, ``Using six moments of Boltzmann’s transport equation for device simulation,'' Journal of Applied Physics, vol. 90, no. 5, pp. 2389-2396, 2001.

131

R. Stratton, ``Diffusion of hot and cold electrons in semiconductor barriers,'' Physical Review, vol. 126, no. 6, pp. 2002-2014, 1962.

132

K. Bløtekjær, ``Transport equations for electrons in two-valley semiconductors,'' IEEE Transactions on Electron Devices, vol. 17, no. 1, pp. 38-47, 1970.

133

T. Grasser and S. Selberherr, ``Limitations of hydrodynamic and energy-transport models,'' in Proceedings International Workshop on the Physics of Semiconductor Devices (IWPSD), pp. 584-591, 2001.

134

T. Grasser, H. Kosina, C. Heitzinger, and S. Selberherr, ``Characterization of the hot electron distribution function using six moments,'' Journal of Applied Physics, vol. 91, no. 6, pp. 3869-3879, 2002.

135

T. Grasser, C. Jungemann, H. Kosina, B. Meinerzhagen, and S. Selberherr, ``Advanced transport models for sub-micrometer devices,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 1-8, 2004.

136

V. Sverdlov, E. Ungersboeck, H. Kosina., and S. Selberherr, ``Current transport models for nanoscale semiconductor devices,'' Materials Science and Engineering: R: Reports, vol. 58, no. 6, pp. 228-270, 2008.

137

S. Vitanov, V. Palankovski, R. Quay, and E. Langer, ``Two-dimensional numerical simulation of AlGaN/GaN HEMTs,'' in Book of Proceedings TARGET Days, pp. 81-84, 2006.

138

S. Selberherr, W. Hänsch, M. Seavey, and J. Slotboom, ``The evolution of the MINIMOS mobility model,'' Solid-State Electronics, vol. 33, no. 11, pp. 1425-1436, 1990.

139

C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, ``A physically based mobility model for numerical simulation of nonplanar devices,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 11, pp. 1164-1171, 1988.

140

V. M. J. Agostinelli, H. Shin, and A. F. J. Tasch, ``A comprehensive model for inversion layer hole mobility for simulation of submicrometer MOSFET's,'' IEEE Transactions on Electron Devices, vol. 38, no. 1, pp. 151-159, 1991.

141

M. Darwish, J. Lentz, M. Pinto, P. Zeitzoff, T. Krutsick, and H. H. Vuong, ``An improved electron and hole mobility model for general purpose device simulation,'' IEEE Transactions on Electron Devices, vol. 44, no. 9, pp. 1529-1538, 1997.

142

B. Neinhüs, C. Nguyen, C. Jungemann, and B. Meinerzhagen, ``A CPU efficient electron mobility model for MOSFET simulation with quantum corrected charge densities,'' in Proceedings European Solid-State Device Research Conference (ESSDERC), pp. 332-335, 2000.

143

T. Grasser, R. Entner, O. Triebl, H. Enichlmair, and R. Minixhofer, ``TCAD modeling of negative bias temperature instability,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 330-333, 2006.

144

V.-H. Chan and J. Chung, ``Two-stage hot-carrier degradation and its impact on submicrometer LDD NMOSFET lifetime prediction,'' IEEE Transactions on Electron Devices, vol. 42, no. 5, pp. 957-962, 1995.

145

S. Sun and J. Plummer, ``Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,'' IEEE Transactions on Electron Devices, vol. 27, no. 8, pp. 1497-1508, 1980.

146

H.-S. Wong, M. White, J. Krutsick, and R. Booth, ``Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET’s,'' Solid-State Electronics, vol. 30, no. 9, pp. 953-968, 1987.

147

D. Caughey and R. Thomas, ``Carrier mobilities in silicon empirically related to doping and field,'' Proceedings of the IEEE, vol. 55, no. 12, pp. 2192-2193, 1967.

148

R. Jaggi and H. Weibel, ``High-field electron drift velocities and current densities in silicon,'' Helvetica Physica Acta, vol. 42, pp. 631-632, 1969.

149

R. Jaggi, ``High-field drift velocities in silicon and germanium,'' Helvetica Physica Acta, vol. 42, pp. 941-943, 1969.

150

S. Dhar, H. Kosina, G. Karlowatz, S. E. Ungersboeck, T. Grasser, and S. Selberherr, ``High-field electron mobility model for strained-silicon devices,'' IEEE Transactions on Electron Devices, vol. 53, no. 12, pp. 3054-3062, 2006.

151

T. Grasser and M. Karner, Modellierung elektronischer Bauelemente.
Institute for Microelectronics, TU Vienna, 2006.
Lecture Notes.

152

W. Shockley and W. Read, ``Statistics of the recombinations of holes and electrons,'' Physical Review, vol. 87, no. 5, pp. 835-842, 1952.

153

R. Hall, ``Electron-hole recombination in germanium,'' Physical Review, vol. 87, no. 2, p. 387, 1952.

154

D. Fleetwood, H. Xiong, Z.-Y. Lu, C. Nicklaw, J. Felix, R. Schrimpf, and S. Pantelides, ``Unified model of hole trapping, 1/f noise, and thermally stimulated current in MOS devices,'' IEEE Transactions on Nuclear Science, vol. 49, no. 6, pp. 2674-2683, 2002.

155

J. Brugler and P. Jespers, ``Charge pumping in MOS devices,'' IEEE Transactions on Electron Devices, vol. 16, no. 3, pp. 297-302, 1969.

156

P. Habas and S. Selberherr, ``A closed-loop extraction of the spatial distribution of interface traps based on numerical model of the charge-pumping experiment,'' in Proceedings Solid State Devices and Materials (SSDM), pp. 170-172, 1992.

157

J. Dziewior and W. Schmid, ``Auger coefficients for highly doped and highly excited silicon,'' Applied Physics Letters, vol. 31, no. 5, pp. 346-348, 1977.

158

L. Huldt, N. G. Nilsson, and K. G. Svantesson, ``The temperature dependence of band-to-band Auger recombination in silicon,'' Applied Physics Letters, vol. 35, no. 10, pp. 776-777, 1979.

159

G. Hurkx, D. Klaassen, and M. Knuvers, ``A new recombination model for device simulation including tunneling,'' IEEE Transactions on Electron Devices, vol. 39, no. 2, pp. 331-338, 1992.

160

H.-M. Lee, C.-J. Liu, C.-W. Hsu, M.-S. Liang, Y.-C. King, and C.-H. Hsu, ``New trap-assisted band-to-band tunneling induced gate current model for p-channel metal-oxide-semiconductor field effect transistors with sub-3 nm oxides,'' Japanese Journal of Applied Physics, vol. 40, pp. 1218-1221, 2001.

161

J. Whitfield, C. Gill, J. Yang, H. Xu, C. Zhan, B. Baumert, and M. Zunino, ``ESD MM failures resulting from transient reverse currents,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 136-139, 2006.

162

V. d'Alessandro and N. Rinaldi, ``A critical review of thermal models for electro-thermal simulation,'' Solid-State Electronics, vol. 46, no. 4, pp. 487-496, 2002.

163

P. Galy, V. Berland, B. Foucher, A. Guilhaume, J. Chante, S. Bardy, and F. Blanc, ``Experimental and 3D simulation correlation of a gg-nMOS transistor under high current pulse,'' Microelectronics Reliability, vol. 42, no. 9-11, pp. 1299-1302, 2002.

164

H. Xie, R. Zhan, A. Wang, and R. Gafiteanu, ``Real 3D electro-thermal simulation and analysis for ESD protection structures,'' in Proceedings IEEE Devices, Circuits and Systems, vol. 1, pp. 61-64, 2004.

165

S. Gaur and D. Navon, ``Two-dimensional carrier flow in a transistor structure under nonisothermal conditions,'' IEEE Transactions on Electron Devices, vol. 23, no. 1, pp. 50-57, 1976.

166

M. Adler, ``Accurate calculations of the forward drop and power dissipation in thyristors,'' IEEE Transactions on Electron Devices, vol. 25, no. 1, pp. 16-22, 1978.

167

J. Slotboom and H. de Graaff, ``Bandgap narrowing in silicon bipolar transistors,'' IEEE Transactions on Electron Devices, vol. 24, no. 8, pp. 1123-1125, 1977.

168

S. Selberherr and E. Langer, ``Low temperature MOS device modeling,'' in Proceedings Workshop On Low Temperature Semiconductor Electronics, pp. 68-72, 1989.

169

R. Tsu and L. Esaki, ``Tunneling in a finite superlattice,'' Applied Physics Letters, vol. 22, no. 11, pp. 562-564, 1973.

170

R. H. Fowler and L. Nordheim, ``Electron emission in intense electric fields,'' Proceedings Royal Society A, vol. 119, no. 781, pp. 173-181, 1928.

171

M. Herrmann and A. Schenk, ``Field and high-temperature dependence of the long term charge loss in erasable programmable read only memories: Measurements and modeling,'' Journal of Applied Physics, vol. 77, no. 9, pp. 4522-4540, 1995.

172

R. Entner, T. Grasser, S. Selberherr, A. Gehring, and H. Kosina, ``Modeling of tunneling currents for highly degraded CMOS devices,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 219-222, 2005.

173

M. Wagner, M. Karner, and T. Grasser, ``Quantum correction models for modern semiconductor devices,'' in Proceedings International Workshop on the Physics of Semiconductor Devices (IWPSD), vol. 1, pp. 458-461, 2005.

174

G. Paasch and H. Übensee, ``A modified local density approximation,'' Physica status solidi (b), vol. 113, no. 1, pp. 165-178, 1982.

175

W. Hänsch, T. Vogelsang, R. Kircher, and M. Orlowski, ``Carrier transport near the Si/SiO$_2$ interface of a MOSFET,'' Solid-State Electronics, vol. 32, no. 10, pp. 839-849, 1989.

176

M. van Dort, P. Woerlee, and A. Walker, ``A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions,'' Solid-State Electronics, vol. 37, no. 3, pp. 411-414, 1994.

177

M. Vasicek, Advanced Macroscopic Transport Models.
Dissertation, Technische Universität Wien, Oktober 2009.
http://www.iue.tuwien.ac.at/phd/vasicek/.

178

V. Palankovski, Simulation of Heterojunction Bipolar Transistors.
Dissertation, Technische Universität Wien, 2000.
http://www.iue.tuwien.ac.at/phd/palankovski/.

179

J. Slotboom, G. Streutker, M. van Dort, P. Woerlee, A. Pruijmboom, and D. Gravesteijn, ``Non-local impact ionization in silicon devices,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 127-130, 8-11 Dec. 1991.

180

D. Cassi and B. Riccò, ``An analytical model of the energy distribution of hot electrons,'' IEEE Transactions on Electron Devices, vol. 37, no. 6, pp. 1514-1521, 1990.

181

A. Concannon, F. Piccinini, A. Mathewson, and C. Lombardi, ``The numerical simulation of substrate and gate currents in MOS and EPROMs,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 289-292, 1995.

182

T. Grasser, H. Kosina, and S. Selberherr, ``Influence of the distribution function shape and the band structure on impact ionization modeling,'' Journal of Applied Physics, vol. 90, no. 12, pp. 6165-6171, 2001.

183

A. Gehring, Simulation of Tunneling in Semiconductor Devices.
Dissertation, Technische Universität Wien, November 2003.
http://www.iue.tuwien.ac.at/phd/gehring/.

184

P. G. Scrobohaci and T.-B. Tang, ``Modeling of the hot electron subpopulation and its application to impact ionization in submicron silicon devices-Part I: transport equations,'' IEEE Transactions on Electron Devices, vol. 41, no. 7, pp. 1197-1205, 1994.

185

K. Sonoda, S. Dunham, M. Yamaji, K. Taniguchi, and C. Hamaguchi, ``Impact ionization model using average energy and average square energy of distribution function,'' Japanese Journal of Applied Physics, vol. 35, no. 2B, pp. 818-825, 1996.

186

T. Grasser, H. Kosina, and S. Selberherr, ``Hot carrier effects within macroscopic transport models,'' International Journal of High Speed Electronics and Systems, vol. 13, no. 3, pp. 873-901, 2003.

187

T. Grasser, H. Kosina, C. Heitzinger, and S. Selberherr, ``Accurate impact ionization model which accounts for hot and cold carrier populations,'' Applied Physics Letters, vol. 80, no. 4, pp. 613-615, 2002.

188

G. Karlowatz, E. Ungersboeck, W. Wessner, and H. Kosina, ``Full-band Monte Carlo analysis of electron transport in arbitrarily strained silicon,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 63-66, 6-8 Sept. 2006.

189

R. van Overstraeten and H. de Man, ``Measurement of the ionization rates in diffused silicon p-n junctions,'' Solid-State Electronics, vol. 13, no. 5, pp. 583-608, 1970.

190

Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices.
Cambridge University Press, 1998.

191

A. G. Chynoweth, ``Ionization rates for electrons and holes in silicon,'' Physical Review, vol. 109, pp. 1537-1540, Mar 1958.

192

W. Shockley, ``Problems related to p-n junctions in silicon,'' Solid-State Electronics, vol. 2, no. 1, pp. 35-67, 1961.

193

P. A. Wolff, ``Theory of electron multiplication in silicon and germanium,'' Physical Review, vol. 95, no. 6, pp. 1415-1420, 1954.

194

Synopsys, Inc., originally published by ISE, ISE TCAD Release 9.5 - ATLAS, 2003.

195

G. A. Baraff, ``Distribution functions and ionization rates for hot electrons in semiconductors,'' Physical Review, vol. 128, no. 6, pp. 2507-2517, 1962.

196

C. R. Crowell and S. M. Sze, ``Temperature dependence of avalanche multiplication in semiconductors,'' Applied Physics Letters, vol. 9, no. 6, pp. 242-244, 1966.

197

A. Sutherland, ``An improved empirical fit to Baraff's universal curves for the ionization coefficients of electron and hole multiplication in semiconductors,'' IEEE Transactions on Electron Devices, vol. 27, no. 7, pp. 1299-1300, 1980.

198

T. Lackner, ``Avalanche multiplication in semiconductors: A modification of Chynoweth's law,'' Solid-State Electronics, vol. 34, no. 1, pp. 33-42, 1991.

199

J. Slotboom, G. Streutker, G. Davids, and P. Hartog, ``Surface impact ionization in silicon devices,'' in Technical Digest International Electron Devices Meeting (IEDM), vol. 33, pp. 494-497, 1987.

200

M. van Dort, J. Slotboom, G. Streutker, and P. Woerlee, ``Lifetime calculations of MOSFETs using depth-dependent non-local impact ionization,'' Microelectronics Journal, vol. 26, pp. 301-305, 1995.

201

C. Jungemann, S. Yamaguchi, and H. Goto, ``Is there experimental evidence for a difference between surface and bulk impact ionization in silicon?,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 383-386, 1996.

202

Y. Okuto and C. R. Crowell, ``Ionization coefficients in semiconductors: A nonlocalized property,'' Physical Review B, vol. 10, no. 10, pp. 4284-4296, 1974.

203

C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, ``Hot-electron-induced MOSFET degradation - model, monitor, and improvement,'' IEEE Transactions on Electron Devices, vol. 32, no. 2, pp. 375-385, 1985.

204

Y. A. El-Mansy and D. M. Caughey, ``Modelling weak avalanche multiplication currents in IGFETs and SOS transistors for CAD,'' in Technical Digest International Electron Devices Meeting (IEDM), vol. 21, pp. 31-34, 1975.

205

B. Meinerzhagen, ``Consistent gate and substrate current modeling based on energy transport and the lucky electron concept,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 504-507, 1988.

206

K. Katayama and T. Toyabe, ``A new hot carrier simulation method based on full 3d hydrodynamic equations,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 135-138, 1989.

207

Y. Apanovich, E. Lyumkis, B. Polsky, A. Shur, and P. Blakey, ``Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 6, pp. 702-711, 1994.

208

F. M. Bufler, Y. Asahi, H. Yoshimura, C. Zechner, A. Schenk, and W. Fichtner, ``Monte Carlo simulation and measurement of nanoscale n-MOSFETs,'' IEEE Transactions on Electron Devices, vol. 50, no. 2, pp. 418-424, 2003.

209

L. Keldysh, ``Concerning the theory of impact ionization in semiconductors,'' Soviet Physics JETP, vol. 21, pp. 1135-1144, 1965.

210

Y. Kamakura, H. Mizuno, M. Yamaji, M. Morifuji, K. Taniguchi, C. Hamaguchi, T. Kunikiyo, and M. Takenaka, ``Impact ionization model for full band Monte Carlo simulation,'' Journal of Applied Physics, vol. 75, no. 7, pp. 3500-3506, 1994.

211

G. La Rosa and S. E. Rauch, III, ``Channel hot carrier effects in n-MOSFET devices of advanced submicron CMOS technologies,'' Microelectronics Reliability, vol. 47, no. 4-5, pp. 552-558, 2007.

212

S. E. Rauch, III, F. J. Guarin, and G. La Rosa, ``Impact of e-e scattering to the hot carrier degradation of deep submicron NMOSFETs,'' IEEE Electron Device Letters, vol. 19, no. 12, pp. 463-465, 1998.

213

S. E. Rauch, III, G. La Rosa, and F. J. Guarin, ``Role of e-e scattering in the enhancement of channel hot carrier degradation of deep sub-micron NMOSFETs at high V $_\mathrm{GS}$ conditions,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 399-405, 2001.

214

I. Starkov, S. Tyaginov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.-M. Park, H. Enichlmair, M. Karner, C. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, and T. Grasser, ``Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band Monte-Carlo simulations,'' in Proceedings IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 1-6, 2010.

215

S. E. Rauch, III and G. La Rosa, ``The energy driven paradigm of NMOSFET hot carrier effects,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 708-709, 2005.

216

J. G. Kassakian and D. J. Perreault, ``The future of electronics in automobiles,'' in Proceedings International Symposium on Power Semiconductor Devices and IC's (ISPSD), pp. 15-19, 2001.

217

T. Maloney and N. Khurana, ``Transmission line pulsing techniques for circuit modeling,'' in Electrical Overstress/Electrostatic Discharge Symposium Proceedings, pp. 49-54, 1985.

218

Z. Yu, D. Chen, R. J. G. Goossens, R. W. Dutton, P. Vande Voorde, and S.-Y. Oh, ``Accurate modeling and numerical techniques in simulation of impact-ionization effects on BJT characteristics,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 901-904, 1991.

219

R. J. G. Goossens, S. Beebe, Z. Yu, and R. Dutton, ``An automatic biasing scheme for tracing arbitrarily shaped I-V curves,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 3, pp. 310-317, 1994.

220

M. Bartels, S. Decker, B. Neinhus, and B. Meinerzhagen, ``A robust curve tracing scheme for the simulation of bipolar breakdown characteristics with nonlocal impact ionization models,'' in Proceedings European Solid-State Device Research Conference (ESSDERC), vol. 1, pp. 492-495, 1999.

221

C. Salaméro, N. Nolhier, A. Gendron, M. Bafleur, P. Besse, and M. Zécri, ``TCAD methodology for ESD robustness prediction of smart power ESD devices,'' IEEE Transactions on Device and Materials Reliability, vol. 6, no. 3, pp. 399-407, 2006.

222

E. Takeda, N. Suzuki, and T. Hagiwara, ``Device performance degradation due to hot-carrier injection at energies below the Si-SiO$_2$ energy barrier,'' in Technical Digest International Electron Devices Meeting (IEDM), vol. 29, pp. 396-399, 1983.

223

A. Bravaix, C. Guerin, V. Huard, D. Roy, J. M. Roux, and E. Vincent, ``Hot-carrier acceleration factors for low power managemenet in DC-AC stressed 40nm NMOS node at high temperature,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 531-548, 2009.

224

W. Qin, W. Chim, D. Chan, and C. Lou, ``Modelling the degradation in the subthreshold characteristics of submicrometre LDD PMOSFETs under hot-carrier stressing,'' Semiconductor Science and Technology, vol. 13, p. 453, 1998.

225

S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, ``Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor,'' IEEE Transactions on Electron Devices, vol. 27, no. 8, pp. 1359-1367, 1980.

226

T.-Y. Huang, ``Effects of channel shapes on MOSFET hot-electron resistance,'' Electronics Letters, vol. 21, no. 5, pp. 211-212, 1985.

227

F.-C. Hsu and H. R. Grinolds, ``Structure-enhanced MOSFET degradation due to hot-electron injection,'' IEEE Electron Device Letters, vol. 5, no. 3, pp. 71-74, 1984.

228

T. Mizuno, A. Toriumi, M. Iwase, M. Takahashi, H. Niiyama, M. Fukumoto, and M. Yoshimi, ``Hot-carrier effects in 0.1 $\mu$ m gate length CMOS devices,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 695-698, 1992.

229

E. Li, E. Rosenbaum, J. Tao, G. C.-F. Yeap, M.-R. Lin, and P. Fang, ``Hot carrier effects in nMOSFETs in 0.1 $\mu$ m CMOS technology,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 253-258, 1999.

230

K. Hess, L. F. Register, B. Tuttle, J. Lyding, and I. C. Kizilyalli, ``Impact of nanostructure research on conventional solid-state electronics: The giant isotope effect in hydrogen desorption and CMOS lifetime,'' Physica E, vol. 3, no. 1-3, pp. 1-7, 1998.

231

W. McMahon, K. Matsuda, J. Lee, K. Hess, and J. Lyding, ``The effects of a multiple carrier model of interface trap generation on lifetime extraction for MOSFETs,'' in Proceedings NSTI-Nanotech, vol. 1, pp. 576-579, 2002.

232

P. Avouris, R. E. Walkup, A. R. Rossi, T.-C. Shen, G. C. Abeln, J. R. Tucker, and J. W. Lyding, ``STM-induced H atom desorption from Si(100): isotope effects and site selectivity,'' Chemical Physics Letters, vol. 257, no. 1-2, pp. 148-154, 1996.

233

J. W. Lyding, K. Hess, G. C. Abeln, D. S. Thompson, J. S. Moore, M. C. Hersam, E. T. Foley, J. Lee, Z. Chen, S. T. Hwang, H. Choi, P. Avouris, and I. C. Kizilyalli, ``Ultrahigh vacuum–scanning tunneling microscopy nanofabrication and hydrogen/deuterium desorption from silicon surfaces: implications for complementary metal oxide semiconductor technology,'' Applied Surface Science, vol. 130-132, pp. 221-230, 1998.

234

R. Biswas, Y.-P. Li, and B. C. Pan, ``Enhanced stability of deuterium in silicon,'' Applied Physics Letters, vol. 72, no. 26, pp. 3500-3502, 1998.

235

K. Hess, L. Register, W. McMahon, B. Tuttle, O. Aktas, U. Ravaioli, J. Lyding, and I. Kizilyalli, ``Theory of channel hot-carrier degradation in MOSFETs,'' Physica B, vol. 272, no. 1-4, pp. 527-531, 1999.

236

K. Hess, A. Haggag, W. McMahon, B. Fischer, K. Cheng, J. Lee, and J. Lyding, ``Simulation of Si-SiO$_2$ defect generation in CMOS chips: from atomistic structure to chip failure rates,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 93-96, 2000.

237

E. Takeda and N. Suzuki, ``An empirical model for device degradation due to hot-carrier injection,'' IEEE Electron Device Letters, vol. 4, no. 4, pp. 111-113, 1983.

238

J.-S. Goo, Y.-G. Kim, H. L'Yee, H.-Y. Kwon, and H. Shin, ``An analytical model for hot-carrier-induced degradation of deep-submicron n-channel LDD MOSFETs,'' Solid-State Electronics, vol. 38, no. 6, pp. 1191-1169, 1995.

239

R. Dreesen, K. Croes, J. Manca, W. De Ceuninck, L. De Schepper, A. Pergoot, and G. Groeseneken, ``Modelling hot-carrier degradation of LDD NMOSFETs by using a high-resolution measurement technique,'' Microelectronics Reliability, vol. 39, no. 6-7, pp. 785-790, 1999.

240

S. Tyaginov, I. Starkov, H. Enichlmair, J.-M. Park, C. Jungemann, and T. Grasser, ``Physics-based hot-carrier degradation models,'' ECS Transactions, vol. 35, no. 4, pp. 321-352, 2011.

241

W. McMahon, L. F. Register, and K. Hess, ``Effect of disorder-induced variations among the bond energies of passivated silicon dangling bonds on the time-dependence of nMOSFET degradation,'' in Annual March Meeting American Physical Society, 2000.

242

A. Haggag, K. Hess, W. McMahon, and L. F. Register, ``Impact of scaling on CMOS IC failure rate and design rules for reliability,'' in Proceedings International Workshop of Computational Electronics (IWCE), pp. 49-50, 2000.

243

S. E. Rauch, III and G. La Rosa, ``CMOS hot carrier: From physics to end of life projections, and qualification,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), 2010.

244

C. Guerin, V. Huard, and A. Bravaix, ``The energy-driven hot carrier degradation modes,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 692-693, 2007.

245

S. Tyaginov, I. Starkov, O. Triebl, J. Cervenka, C. Jungemann, S. Carniello, J.-M. Park, H. Enichlmair, M. Karner, C. Kernstock, E. Seebacher, R. Minixhofer, H. Ceric, and T. Grasser, ``Interface traps density-of-states as a vital component for hot-carrier degradation modeling,'' Microelectronics Reliability, vol. 50, no. 9-11, pp. 1267-1272, 2010.

246

P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, ``A novel hot-hole injection degradation model for lateral nDMOS transistors,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 39.6.1-39.6.4, 2001.

247

P. Moens, J. Mertens, F. Bauwens, P. Joris, W. De Ceuninck, and M. Tack, ``A comprehensive model for hot carrier degradation in LDMOS transistors,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 492-497, 2007.

248

I. Starkov, H. Enichlmair, S. Tyaginov, and T. Grasser, ``Analysis of the threshold voltage turn-around effect in high-voltage n-MOSFETs due to hot-carrier stress,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. XT.7.1-XT.7.6, 2012.

249

I. Starkov, H. Ceric, H. Enichlmair, J.-M. Park, S. Tyaginov, T. Grasser, and C. Jungemann, ``Analysis of worst-case hot-carrier degradation conditions in the case of n- and p-channel high-voltage MOSFETs,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 127-130, 2011.

250

M. Bina, K. Rupp, S. Tyaginov, O. Triebl, and T. Grasser, ``Modeling of hot carrier degradation using a spherical harmonics expansion of the bipolar Boltzmann transport equation,'' in Technical Digest International Electron Devices Meeting (IEDM), 2012.
(in print).

251

D. DiMaria and J. Stasiak, ``Trap creation in silicon dioxide produced by hot electrons,'' Journal of Applied Physics, vol. 65, no. 6, pp. 2342-2356, 1989.

252

P. Hehenberger, T. Aichinger, T. Grasser, W. Gös, O. Triebl, B. Kaczer, and M. Nelhiebel, ``Do NBTI-induced interface states show fast recovery? A study using a corrected on-the-fly charge-pumping measurement technique,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 1033-1038, 2009.

253

T. Grasser, H. Reisinger, P. Wagner, F. Schanovsky, W. Gös, and B. Kaczer, ``The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability,'' in Proceedings IEEE International Reliability Physics Symposium (IRPS), pp. 16-25, 2010.

254

T. Grasser, B. Kaczer, W. Gös, H. Reisinger, T. Aichinger, P. Hehenberger, P. Wagner, F. Schanovsky, J. Franco, P. Roussel, and M. Nelhiebel, ``Recent advances in understanding the bias temperature instability,'' in Technical Digest International Electron Devices Meeting (IEDM), pp. 4.4.1-4.4.4, 2010.

255

P. Fleischmann, Mesh Generation for Technology CAD in Three Dimensions.
Dissertation, Technische Universität Wien, 1999.
http://www.iue.tuwien.ac.at/phd/fleischmann/.

256

A. Okabe, B. Boots, and K. Sugihara, Spatial Tessellations.
John Wiley and Sons Ltd, 1992.

257

L. P. Chew, ``Create a Voronoi diagram or Delaunay triangulation by clicking points,'' 2007.
http://www.cs.cornell.edu/home/chew/Delaunay.html.

258

M. Spevak, R. Heinzl, P. Schwaha, and T. Grasser, ``Simulation of microelectronic structures using a posteriori error estimation and mesh optimization,'' in 5th Mathmod Vienna Proceedings, pp. 5.1-5.8, 2006.

259

R. Bank, D. Rose, and W. Fichtner, ``Numerical methods for semiconductor device simulation,'' IEEE Transactions on Electron Devices, vol. 30, no. 9, pp. 1031-1041, 1983.

260

Z. Stanojević, M. Karner, K. Schnass, C. Kernstock, O. Baumgartner, and H. Kosina, ``A versatile finite volume simulator for the analysis of electronic properties of nanostructures,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 143-146, 2011.

261

S. J. Polak, C. den Heijer, and W. Schilders, ``Semiconductor device modelling from the numerical point of view,'' International Journal for Numerical Methods in Engineering, vol. 24, pp. 763-838, 1987.

262

O. Triebl and T. Grasser, ``Investigation of vector discretization schemes for box volume methods,'' in Proceedings NSTI-Nanotech, vol. 3, pp. 61-64, 2007.

263

S. Laux and B. Grossman, ``A general control-volume formulation for modeling impact ionization in semiconductor transport,'' IEEE Transactions on Electron Devices, vol. 32, no. 10, pp. 2076-2082, 1985.

264

J. Bürgler, R. Bank, W. Fichtner, and R. Smith, ``A new discretization scheme for the semiconductor current continuity equations,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 5, pp. 479-489, 1989.

265

Synopsys, Inc., originally published by ISE, ISE TCAD Release 9.5 - DESSIS, 2003.

266

H. Shao, Numerical Analysis of Meshing and Discretization for Anisotropic Convection-Diffusion Equations with Applications.
Dissertation, Duke University, Aug. 1999.

267

M. Patil, ``New discretization scheme for two-dimensional semiconductor device simulation on triangular grid,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 11, pp. 1160-1165, 1998.

268

Y. He and G. Cao, ``A generalized Scharfetter-Gummel method to eliminate crosswind effects,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 12, pp. 1579-1582, 1991.

269

W. Allegretto, A. Nathan, and H. Baltes, ``Numerical analysis of magnetic-field-sensitive bipolar devices,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 4, pp. 501-511, 1991.

270

H. Kosina, O. Triebl, and T. Grasser, ``Box method for the convection-diffusion equation based on exponential shape functions,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), vol. 12, pp. 317-320, 2007.

271

O. Triebl and T. Grasser, ``Vector discretization schemes in technology CAD environments,'' Romanian Journal of Information Science and Technology, vol. 10, no. 2, pp. 167-176, 2007.

272

C. Fischer, Bauelementsimulation in einer computergestützten Entwurfsumgebung.
Dissertation, Technische Universität Wien, May 1994.
http://www.iue.tuwien.ac.at/phd/fischer/.

273

O. Schenk, M. Hagemann, and S. Rollin, ``Recent advances in sparse linear solver technology for semiconductor device simulation matrices,'' in Proceedings Simulation of Semiconductor Processes and Devices (SISPAD), pp. 103-108, 2003.

274

P. Deuflhard, ``A modified Newton method for the solution of ill-conditioned systems of nonlinear equations with application to multiple shooting,'' Numerische Mathematik, vol. 22, pp. 289-315, 1974.

275

V. Axelrad, ``Grid quality and its influence on accuracy and convergence in device simulation,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 2, pp. 149-157, 1998.

276

N. Shigyo, H. Tanimoto, and T. Enda, ``Mesh related problems in device simulation: Treatments of meshing noise and leakage current,'' Solid-State Electronics, vol. 44, pp. 11-16, 2000.