D I S S E R T A T I O N
Mixed Negative Bias Temperature Instability and Hot-Carrier Stress
ausgeführt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften
unter der Leitung von
Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Tibor GRASSER
Institut für Mikroelektronik
eingereicht an der Technischen Universität Wien
Fakultät für Elektrotechnik und Informationstechnik
von
Dipl.-Ing. Bianka ULLMANN
0425601 / E 786 710
Wien, am 28. Mai 2018
Bias temperature instability (BTI) and hot-carrier degradation (HCD) are among the most important reliability issues, which affect the performance of metal-oxide-semicon-ductor field-effect transistors (MOSFETs). Both are typically studied in an idealized setting. In particular, for BTI studies no voltage is applied to the drain, leading to laterally homogeneous degradation. With increasing drain bias, the degradation becomes more and more inhomogeneous and the contribution of HCD to the total degradation increases. Even though it is well understood that this mixed BTI/hot-carrier (HC) degradation corresponds to what actually happens in real circuits, there is only a limited number of studies available on the impact of the mixed stress conditions.
In this thesis, the problem of mixed negative bias temperature instability (NBTI)/hot-carrier (HC) stress conditions on SiON pMOSFET characteristics is discussed. This contains on the one hand a comparison of commonly used measurement methods for the threshold voltage shift: the single point measurement of the drain current and the gate voltage. It is shown that in the case of mixed NBTI/HC stress both methods provide different results for the shift, which has to be considered when modeling the degradation. On the other hand, the focus is on the contribution of single defects to the recoverable component of the threshold voltage degradation. Quite remarkably, mixed NBTI/HC stress affects the recoverable component considerably due to two effects.
First, the contribution of oxide defects to recovery after mixed NBTI/HC stress is suppressed independently of their lateral position. As an explanation, from an electrostatic point of view, recovery after mixed NBTI/HC stress is mainly attributed to charge carrier emissions by oxide defects near the source, which have been charged during stress. However, the experimental characterization of recovery after different stress conditions clearly suggests that even defects located in the vicinity of the source can remain uncharged after mixed NBTI/HC stress and thus do not contribute to the recovery signal although they are fully charged after homogeneous NBTI stress. As a consequence, recovery of the threshold voltage shift can be negligibly small after certain stress conditions. This leads to the conclusion that a simple electrostatic model neither describes the behavior of degradation during mixed NBTI/HC stress nor the recovery afterwards properly. Only if secondary generated carriers triggered by impact ionization and the carrier distribution functions are correctly considered, agreement with experimental data is obtained.
Second, the experimental data collected during this work shows that the contribution of oxide defects to the recoverable component depends strongly on the device “history". The experimental characterization shows that mixed NBTI/HC stress anneals a considerable number of oxide defects and thus dramatically reduces recovery after all kinds of stress conditions, homogeneous NBTI and mixed NBTI/HC. In this context, volatility as a possible mechanism responsible for such a reducution is discussed.
As a conclusion, both degradation mechanisms, NBTI and HCD have an impact on each other. This impact depends on both, stress conditions which trigger physical mechanisms associated with NBTI as well as HCD and previoiusly applied stress or in other words the “history".
Die Zuverlässigkeit von einzelnen Elektronikkomponenten ist unter anderem von bias temperature instability (BTI) und hot-carrier degradation (HCD) beeinflusst. Diese Degradationsmechanismen beeinflussen die Leistungsfähigkeit von einem der wichtigsten Bauteile in elektronischen Schaltkreisen, nämlich dem metal-oxide-semiconductor field-effect transistor (MOSFET). Typischerweise werden BTI und HCD unabhängig voneinander erforscht. Zum Beispiel wird BTI unter homogenen Bedingungen charakterisiert, indem keine Spannung am Drain-Kontakt angelegt wird. Sobald die Spannung am Drain-Kontakt erhöht wird, herrschen immer inhomogenere Bedingungen vor, was zu einem wachsenden Beitrag von HCD zur Gesamtdegradation führt. Obwohl es bekannt ist, dass eine solche gemischte BTI/hot-carrier (HC) Degradation den anwendungsrelevantesten Fall darstellt, gibt es wenige Studien zu der Auswirkung auf die MOSFET-Parameter.
In dieser Dissertation wird eine fundierte experimentelle Untersuchung der Auswirkung von gemischtem negative BTI (NBTI)/HC Stress auf SiON pMOSFET Charakteristika präsentiert. Dies beinhaltet einerseits einen Vergleich zwischen zwei gängigen Messmethoden der Schwellspannungsänderung, nämlich der Messung der Gate-Spannung bei konstantem Drain-Strom und der Messung des Drain-Stromes bei konstanter Gate-Spannung. Es wird gezeigt, dass beide Messmethoden unterschiedliche Ergebnisse des zeitlichen Verlaufes der Schwellspannungsänderung nach gemischtem NBTI/HC Stress liefern. Diese Unterschiede werden ausführlich diskutiert. Andererseits liegt der Fokus auf der Untersuchung der ausheilbaren Degradationskomponente. Interessanterweise beeinflusst gemischter NBTI/HC Stress eben diese sehr stark auf Grund von zwei Effekten.
Der erste Effekt ist die Unterdrückung des Beitrags zur ausheilbaren Komponente von einzelnen Materialdefekten im Oxid unabhängig von deren lateralen Positionen. Bisher wurde angenommen, dass das Ausheilen der Schwellspannungsdegradation nur von den elektrostatischen Bedingungen während der Stressphase abhängt. Auf der Einzeldefekt-ebene bedeutet das, dass aufgrund der inhomogenen Bedingungen im Oxid während gemischtem NBTI/HC Stress hauptsächlich Defekte nahe des Source-Kontaktes zur Ausheilung von der Degradation beitragen. Es wird gezeigt, dass diese Annahme nicht stimmt und dass auch der Beitrag von source-seitigen Defekten unterdrückt wird. Dies führt zu einer wesentlich höheren Reduktion der ausheilbaren Degradationskomponente als angenommen. Es wird gezeigt, dass zusätzlich zu den elektrostatischen Bedingungen, im Falle von gemischtem NBTI/HC Stress auch die Ladungsträgerverteilung im Kanal, welche sich auf Grund der inhomogenen Bedingungen und Impact Ionization ändern kann, berücksichtigt werden muss.
Der zweite Effekt betrifft das “Verschwinden" von Defekten auf Grund der Messgeschichte des MOSFETs. Die Experimente zeigen, dass Oxid-Defekte nach vielen Stresszyklen elektrisch inaktiv werden und somit weder zur Degradation, noch zur Ausheilung vom MOSFET beitragen. In diesem Zusammenhang wird der Volatility-Effekt als mögliche Ursache diskutiert.
Zusammenfassend kann gesagt werden, dass beide Mechanismen, NBTI und HCD, einander beeinflussen. Diese Beeinflussung hängt sowohl von den Stressbedingungen, die physikalische Mechanismen auslösen, welche mit NBTI und HCD assoziiert werden, als auch von vergangenem Stress ab.
With the first analysis of electricity more than 200 years ago and the enhanced insight into the physical process of electric charge manipulation the way to revolutionary technological inventions was enabled. Although many inventions were considered fundamental research and initially ignored by industry, some of these have eventually changed our way of living and as such are of enormous economic importance. A rather prominent example is the transistor, which is one of the key inventions of modern society, arguably comparable to the domestication of fire and the invention of the wheel.
As a result of basic research on the physics of solids, transistors were able to replace vacuum tubes in the 1950s. In the following, this led to the development of the integrated circuit and the microprocessor, which are at the heart of modern electronics. Thus, transistors paved the way for a new generation of powerful and efficient electronic devices with a seemingly unlimited number of applications in everyday life. As a consequence of the continuous improvement of their performance, modern technologies have enabled numerous innovative ways of global networking by connecting things and people, optimizing work flows as well as saving valuable resources.
The economic importance of these new technologies and the pressure to keep production costs low have been the driving forces for the development and improvement of the transistor. In 1965, Moore predicted an exponential relationship between circuit complexity (number of transistors per area unit) and time, by stating that “the complexity will double annually." This prediction has in the meantime been revised to a doubling every two years [1], resulting in over 5 billion transistors being processed on a single chip today. As a consequence of the complexity increase, transistors have been downscaled to the deca-nanometer regime during the past decades, which has resulted in reliability issues, power loss and instabilities as the physical limits are approached.
As an introduction to this thesis, a short overview of the consequences that have resulted from downscaling combined with the motivation to study degradation mechanisms in transistors is given.
Since the transistor has been invented, an enormous diversity of transistor technologies has arisen, each of them developed for a different purpose. As examples for the numerous purposes, the basic function of a bipolar junction transistor (BJT) is to amplify current in electronic circuits, the insulated-gate bipolar transistor (IGBT) is a power semiconductor device primarily used as an electronic switch in power electronics and the field-effect transistor (FET) acts like a switch in digital circuits. Particularly the metal-oxide-semiconductor field-effect transistor (MOSFET) is one widely used transistor technology in digital circuits due to the achievable short switching times and the nearly loss-less control at low frequencies. In the present work, MOSFETs were studied exclusively.
Figure 1.1: Lateral planar MOSFET used in complementary MOS (CMOS) technology: The cross section of a p-
channel MOSFET (pMOSFET) is shown in the left panel. Two highly p-doped source and drain regions separated by an n-doped body region (e.g. Si) and an insulating layer (e.g. silicon oxynitride
) separating the gate contact from the body. The right panel shows a circuit schematics
of a CMOS inverter, which is a widly used application of MOSFETs in digital circuits.
The MOSFET in digital circuits can be compared to a switch realized by modifying the conductivity properties of semiconductors. Figure 1.1 shows the cross section of a pMOSFET containing two highly p-doped regions, source and drain, separated by an n-doped body region. An insulating
layer (e.g. amorphous silicon oxynitride ) is sandwiched between the gate and the body, separating them from each other.
Therefore, the gate electrode (metal or polysilicon), the insulating layer and the substrate form the MOSFET capacitor, which prevents a current flow and enables a loss-less control of the MOSFET. Assuming that this capacitor is ideal (no charges in the oxide, resistivity of the oxide is infinite) the MOSFET function can be explained based on the band
diagrams shown in Figure 1.2.
In the case of a pMOSFET, a positive gate voltage () accumulates the majority carriers of
the substrate, which are electrons, in a layer near the oxide/substrate interface. In the band diagram shown in Figure 1.2, this means that the conduction
band (
) bends down towards the Fermi level (
). When sweeping
towards zero, the MOSFET reaches its flatband condition for
0 V (ideal capacitor, otherwise the contact voltage must be
considered), where the majority and minority carriers are in thermal equilibrium. By applying a low negative
the majority carriers are forced away
from the interface and therefore a depletion layer near the interface forms, which results in a bending up of the bands and the intrinsic energy (
) moves closer to
. With further increasing negative
, the depletion layer is populated by
minority carriers until
exceeds a certain threshold voltage (
) and the concentration of minority
carriers is high enough to form a thin inversion layer near the interface. In the band diagram the inversion mode can be explained by a crossing of
and
where the minority carriers exceed the
majority carriers at the interface. In this context it has to be mentioned, that
is defined as a microscopic
parameter which indicates the transition to the inversion mode.
As a consequence, if the supply voltage () is applied between the drain and
the source,
controls the drain
current (
) as seen in the transfer characteristics (
-
) shown in Figure 1.3 for an nMOSFET. If
V, the MOSFET is in its off-state and
current flow is inhibited because of the reverse biased p-n junction. As soon as a positive
is applied and increased an
can flow due to the inverted interface
until it reaches the saturation which corresponds to the on-state of the pMOSFET. This basic function of a MOSFET makes it quite advantageous for processing of
digital signals in circuits as shown in Figure 1.1 for the digital stage of a CMOS inverter. For this example, the nMOSFET is in its on-state in the case that the input is at a digital high level while the pMOSFET is in its off-state. As a result, the output voltage is at ground (digital low
level). By contrast, if the input voltage is near zero, the nMOSFET is in its off-state while the pMOSFET is conductive, which results in an output voltage at
(digital high level). This corresponds
to inverting a digital signal.
Figure 1.3: Typical transfer characteristics of an nMOSFET: Drain current plotted against gate voltage
on a log-lin (red, left scale) and a lin-lin
(blue, right scale) scale. Off-current (current flowing when MOSFET is switched off), subthreshold slope (slope of the subthreshold region in a log-lin plot), threshold voltage (
where the inversion layer is formed) and
on-current (current flowing in the on-state) are the most important parameters characterizing the
-
.
Due to the imperfections of real devices, the CMOS technology allows for deviations from the perfect digital low level at ground and the digital high level at by defining the first as a voltage
between 0 V and
/
and the second as a voltage between
/
and
. Thus, a reliable and proper signal
processing requires digital low and high levels within these margins at a low circuit power consumption, which implies some limitations for the MOSFET design. These limitations can be explained
based on the characteristics of a real device as shown in Figure 1.3. The
-
of a MOSFET is typically characterized by four parameters determined by materials, doping and geometry: the off-current, the sub-threshold swing (
) (reciprocal value of the sub-threshold slope (
) in a log-lin plot),
(in this case a macroscopic
parameter corresponding to, e.g., the gate voltage at which a certain
flows) and the on-current. The
off-current (
0 A at
0 V) is caused by leakage currents between source and drain and is inevitable.
Furthermore, the switching process between off- and on-state shows switching dynamics characterized by
and
which are limited to certain minimum values. At this point it has to be mentioned
that several definitions for the extraction of the macroscopic parameter
exist [2] which contradicts the
definition of
as the gate voltage where inversion is
satisfied. While
as a macroscopic parameter is
extracted from the transfer characteristics and is based, e.g., on an
threshold or on the maximum
transconductance,
as a microscopic parameter defines
the transition from accumulation to inversion. The latter depends on the lateral position due to non-uniform doping profiles along the channel.
These parameters have to meet certain requirements in order to ensure a correct interaction of the MOSFET with other circuit components. For example, clearly distinguishable digital levels require
a ratio between on- and off-current which is as large as possible. This can be achieved by maximizing while simultaneously keeping
and
as low as possible. Besides increasing
the ratio, a high
would also ensure an on-current
which is high enough to drive subsequent digital stages, and low
and
would enhance the switching
dynamics. However, increasing
conflicts with the requirement of low
power consumption since
and, as mentioned in the
previous paragraph,
and
are either fundamental limits or
limited due to materials, doping and geometry of the MOSFET.
The consideration of these aspects in the fabrication process provides fundamental challenges for the design of MOSFETs in general. However, excessive scaling of the MOSFET geometries has led to further challenges.
Figure 1.4: Percolation path: A single percolation path formed by random discrete dopants (current flow shown in the uppermost layer) and contours of constant potential in a pMOSFET: Left: current flow without a disturbance due to charge exchange events caused by oxide defects. Center: reduced current flow when a defect located beside the percolation path traps a charge carrier. Right: disturbance of the current flow when a defect located directly in the center of the percolation path traps a charge carrier. [3]
While decades ago transistor structures were processed in the micrometer range, modern transistor structures have been scaled down to 22 nm in 2008 and to 14 nm or even less in the current generation of
transistors [4]. In addition to the scaling of the gate width () and gate length (
) of the transistors, the oxide thickness (
) has also been scaled down, reaching
values of less than 2 nm, which corresponds in fact to a rather small number of atom layers.
Figure 1.5: Schematic transfer characteristics of a pMOSFET for the three cases shown in Figure 1.4. The more the
current flow is disturbed by a trapped charge carrier, the more shifts, the subthreshold slope decreases
and the on-current reduces.
The scaling of the geometry results in several design and fabrication challenges. For example:
• A short transistor length (less than 100 nm) leads to short-channel effects, e.g., drain-induced barrier lowering, which affects the MOSFET performance. Moreover, channel leakage currents are more pronounced, therefore, the off-current increases significantly
• Considering that the oxide capacitance () is proportional to the ratio between
channel area (
) and
, where
,
has to be downscaled in the same
manner as
. Otherwise,
would increase significantly which
would have a considerable impact on
and the switching dynamics. However,
is limited to a certain minimum value
because of quantum effects like tunneling, leading to a dramatic increase of leakage currents if the oxide thickness is further reduced. With a
below this value, a loss-less control
cannot be ensured any longer.
• As a consequence, the oxide electric field () has increased considerably due to the
indirect proportionality to
.
could be decreased by a decrease of
. However, due to the limited
subthreshold slope, the supply voltages cannot be scaled in the same manner as the device geometry without affecting the ratio between the on- and off-currents. As a consequence, degradation effects depending on
, e.g., the bias
temperature instability (BTI), have a greater impact in downscaled devices than in devices with thicker oxides.
Another consequence of downscaling is a higher device variability due to the variance of parameters between transistors processed in the same manner. This is because nano-scale devices contain, in contrast to large devices, only a
countable number of discrete dopants. Therefore, the slightest deviations of their number or position influence the non-uniform current flow over the width, the so-called percolation path as shown in Figure 1.4 left [3, 5]. Furthermore, the relative deviation of device dimensions due to fabrication variability increases with scaling. As a result of both, the variance of discrete dopants and
dimension deviations, even transistors of the same technology and processed in the same manner show a significant variance in their characteristics, like . This variance results in an
increased ratio between defective and functional devices and affects the performance of circuits detrimentally [6].
Additionally, any real device contains structural defects, for example, impurities, interstitials, vacancies and dangling bonds. Two of the most important defect types are shown in Figure 1.6, interface defects and oxide defects. While both are considered the main cause of device degradation, oxide defects are the main focus of this thesis. Both have energetic states within the band diagram shown in Figure 1.2 and are capable of exchanging charge carriers with the valance or conduction band of the substrate.
Figure 1.6: Two defect types in MOSFETs: Defects can be defined as deviations within the short-range order of the atomic structure. Interface defects occur due to dangling bonds
at the interface between the crystalline substrate and the amorphous oxide. Oxide defects can be either vacancies, e.g., the oxygen vacancy, or bridging atoms, e.g., the bridge, hydroxyl-
center.
Interface defects occur when interfacing different materials, like crystalline and amorphous
. Such material transitions result in an interface region containing trivalent
dangling bonds. Such interface states known as
-centers, which are amphoteric traps and
act as donors as well as acceptors [7, 8]. Typically they act as traps for electrons and holes and distort the device characteristics detrimentally. Charge exchange between interface states and the substrate is consistent with the Shockley-Read-Hall (SRH) theory [9]. In order to ensure a proper MOSFET function, such interface defects have to be reduced considerably. This
reduction is realized by a passivation of the dangling bonds by hydrogen (
) during a processing step of forming gas annealing.
Oxide defects are intrinsic defects and can be either vacancies, e.g., the oxygen vacancy, or bridging atoms, e.g., the bridge. Phenomenologically they are classified in defects near the interface, also called
border defects or defects away from the interface [10, 11]. Microscopically the border defects are often associated with
’ centers, which are trivalent silicon dangling bonds in the oxide [8] or hydrogenic
defects [12]. Similar to the interface defects, defects in the oxide also can distort device characteristics due to charge exchange events with the substrate. Such charge exchange is consistent with non-radiative multiphonon processes
[13–15].
Due to the comparatively large in devices with large
, a single capture or emission event caused by an oxide defect has a small impact on the
MOSFET parameters. In stark contrast, in nano-scale MOSFETs with dimensions around 100 nm or smaller, containing just a handful of defects such events
affect device performance severely [16–18]. Depending on the position of the defect, the percolation path is disturbed as can be seen in the center and right panels of Figure 1.4.
Charge exchange events of defects located near or in the percolation path cause a
shift, a degradation of the
subthreshold slope and a reduction of the on-current as summarized in Figure 1.5. Even one single active defect may shift
by a detrimental value, and thus,
change the transistors behavior and dynamics in digital circuits dramatically. Such a shift of transistor characteristics can endanger the correct interaction with other components, which makes the circuit less reliable and more likely
to fail.
A reliable MOSFET meets the requirement of correct interaction with other circuit components. Unfortunately, even under nominal operating conditions, this correct interaction cannot be ensured at all times. So-called degradation mechanisms, which are associated with shifts of the device characteristics, endanger the correct interaction and reduce the time-to-failure of integrated application. The physical processes responsible for these mechanisms are in the focus of the device reliability research field, including the characterization, understanding and modeling of, e.g., BTI, hot-carrier degradation (HCD), stress induced leakage current (SILC) and trap assisted tunneling. Only with a deep understanding of how degradation is caused, advanced simulations based on realistic models can ensure a robust circuit design. Moreover, such a fundamental knowledge is a great advantage for future transistor designs to prevent instabilities.
The focus of this thesis lies on the experimental characterization of degradation mechanisms. In this context, numerous methods and sequences have been introduced. Each of these methods and sequences is suitable for the characterization of a certain parameter or physical quantity. For example, charge pumping (CP) allows for the characterization of interface defects, whereas time-dependent defect spectroscopy (TDDS) is suitable for the characterization of single oxide defects. The methods and sequences are discussed in Chapter 3 in detail.
In general, degradation has been shown to consist of a recoverable and a permanent component. While, for example, the recoverable component of BTI is attributed to oxide defects, which capture
and emit charge carriers, HCD is suspected to be determined by breakage of passivated Si dangling bonds at the substrate/oxide interface, typically associated with
a permanent component of degradation. Both degradation mechanisms are typically studied in an idealized setting and independently from each other [16, 19–24] as discussed in Chapter 2. In particular, for BTI studies no voltage is applied to the drain, leading to homogeneous degradation. With increasing drain bias, the degradation becomes
more and more inhomogeneous and the contribution of HCD to the total degradation increases. Even though it is well understood that this mixed degradation corresponds to the situation in real
circuits, there is only a limited number of studies available on the impact of the mixed stress conditions [25–27]. Additionally, defect creation, annealing, activation, and deactivation as well as secondarily generated carriers and
non-equilibrium effects play an important role.
The term of degradation is associated with unwanted shifts of certain MOSFET characteristics which can endanger the correct interaction with other circuit components in digital circuits. For
example, drifts of , also called threshold voltage shift (
), during operation seriously
reduce the time-to-failure of integrated applications. Degradation phenomena like stress induced leakage current (SILC), time-dependenc dielectric breakdown (TDDB), bias temperature instability (BTI) and hot-carrier degradation (HCD) describe the origins of these uncontrolled drifts. Especially the
last two are commonly listed as the most prominent challenges which have to be properly understood [4]. In order to meet these challenges, advanced simulations based on physical models are required for a robust design of circuits.
Throughout the process of understanding and modeling degradation mechanisms, different pieces of the puzzle have been put together in order to get the big picture. In this thesis, one important piece of the puzzle in the context of BTI and HCD and their interplay is contributed. Therefore, the theoretical background and state of the art modeling attempts are introduced in this chapter.
The phenomenon BTI has been known for more than 50 years [16, 28–30] and describes basically the temperature and gate bias, or in other words the oxide electric field (), dependent shift of transistor
parameters. For example, at BTI conditions the transconductance (
), the linear
drain current (
), the saturation drain current (
) and the channel mobility (
) decrease while the sub-threshold
swing (
), the off-current and
increase as shown in Figure 2.1. Further, as devices have been downscaled, the vulnerability to BTI has increased. The oxide field at nominal operating conditions has increased due to
the scaling of
, the nominal operating temperature
has increased due to the higher power dissipation, and charge exchange events of single defects have a detrimental impact on the MOSFET electrostatics. All these aspects together with the challenge of
keeping pace with the downscaling of device dimensions have led to several modeling attempts, which are introduced in this section.
Figure 2.1: Transfer characteristics and transconductance of a large-area pMOSFET after negative bias temperature instability (NBTI)
stress: The -
(top) is recorded in the linear region for
drain voltage (
)
−0.1 V and the transconductance is extracted (bottom). After 1 ks
of NBTI stress, the
is shifted and
as well as maximum
transconductance (
) are reduced.
Although BTI affects all device parameters, as it is shown illustratively in Figure 2.1, it is commonly studied and expressed in terms of an
equivalent since BTI affects the threshold voltage significantly. Typically, BTI is characterized as a gate bias is applied to the gate contact while drain, source and well contacts are at ground.
In experiments BTI is classified according to the sign of the gate bias, namely NBTI if a negative
is applied and positive bias temperature instability (PBTI) if a positive
is applied, commonly studied in pMOSFETs and nMOSFETs, respectively. By contrast, the study of NBTI in nMOSFETs and PBTI in pMOSFETs receives less attention due to the difficulty of the experimental characterization. This is because most of the transistors are protected against electrostatic
discharge, which is realized by a diode. This allows only for the operation in inversion mode but not in accumulation. Thus, in most real devices of a commercial technology it is not possible to study NBTI in nMOSFETs and PBTI in pMOSFETs.
Both, NBTI and PBTI, are usually characterized at accelerated stress conditions, which allow for obtaining meaningful parameter shifts within feasible experimental
time slots of minutes, days or weeks instead of years. Such accelerated stress is associated with above nominal operating conditions and
elevated temperatures, e.g., 80 °C to 150 °C. Most of the BTI studies in this regard are realized by the on-the-fly (OTF) method, the measure-stress-measure (MSM) or the extended measure-stress-measure (eMSM) method. Although these methods are discussed in the Sections 3.1, 3.4 and 3.5 in detail, they are introduced in this subsection briefly.
• MSM measurements are realized by short interruptions of the applied gate and drain voltages in order to characterize the degradation state of the device, e.g., by taking an -
curve. From this, the monitored
parameter is extracted and the degradation and/or recovery over time is obtained.
• The OTF method obtains during operation without
interruption of the applied voltages. By a periodic modulation of the gate voltage at stress conditions (
) at a certain
and simultaneous monitoring of
,
can be estimated at a stress
level.
• The eMSM method comprises of basically three phases. First, the unstressed device is characterized by taking an -
. Subsequently,
typically higher than
nominal operating conditions is applied for a certain stress time (
). Finally, the recovery is obtained
with the gate voltage set to recovery conditions (
) near
or below by monitoring the evolution
of
over a certain recovery time (
) without interruption of the applied
voltages.
The impact of a stress and a recovery bias on of a FinFET is illustrated in Figure 2.2. During stress,
drifts and
, being the difference between
the current
and the threshold voltage before stress (
), increases while it decreases again
as soon as the stress is removed. The decrease of
is also called recovery or
relaxation. The sign of
illustrated on a linear scale,
as in Figure 2.2, commonly corresponds to whether an n-channel or a p-channel device is probed and whether the absolute value of
increases or decreases. In the case
that
,
is negative for p-channel
devices and positive for n-channel devices while it has the opposite sign for both in case that
. If
drifts towards larger
, which is typically associated with the term of
degradation,
drifts to more negative
values for p-channel devices and more positive values for n-channel devices. By contrast, the dynamics show the opposite trend if
shifts towards smaller
, which is typically associated with a recovery of the
degradation.
The particular behavior of over time during stress and
recovery strongly depends on whether NBTI or PBTI is applied and on almost every device characteristics and probe condition, namely
,
, temperature,
and
, transistor type and many more. Useful for the further discussion, the most important
dependencies are introduced briefly, starting with the fact that NBTI and PBTI have considerably different impacts on
[32]. A characterization of
these different impacts for an
oxide can be seen in Figure 2.3. While NBTI (
V applied) has the greatest impact on
pMOSFETs, PBTI (
V applied) nearly does not affect nMOSFETs. Based on this, it is not surprising that the most studied case is NBTI on pMOSFETs. In the following, the focus is mainly on
NBTI on pMOSFETs.
Moreover, the evolution of is affected by the gate bias
applied during stress as well as during recovery as illustrated in Figure 2.5. Based on the impact of
and the gate voltage at recovery conditions (
) on
measured for a large-area
pMOSFET it can be seen that while a higher
accelerates the increase
of
over time a higher
suppresses the
recovery of
[33].
Similar to the acceleration of the shift over time due to a higher gate
bias at stress conditions, degradation is also accelerated because of an elevated temperature (
). In this regard, Figure 2.6 shows
that the degradation of
is higher and changes faster
with elevated
[33]. By contrast, the
recovery shows only a weak,
almost negligible, temperature dependence for large-area devices, which is not shown here.
Figure 2.6: Temperature dependence of degradation at the same stress bias: accelerates the degradation of
, which is shown here for a FinFET at three different temperatures (open and closed symbols; two similarly processed wafers). The data is described by a power-law dependence. Figure source: [31].
All shown dependencies on gate bias and temperature are different for different device dimensions and different architectures. While the latter are not discussed in detail here, the changes in device dimensions together with the
limitations in time of the experimental window are quite important in regard of understanding the different approaches of modeling device degradation. For an explanation, one should take a look at the lower limit of the experimental window during stress () of the measurements in
Figure 2.3 and Figure 2.6. This lower limit is 1 s and 10 s, respectively, which are common lower
limits in literature until approximately 2004. The reason lies in the measurement sequences for the characterization of degradation. The interruptions of the applied voltages using the MSM method,
although as short as possible, can take 50 ms or more and disturb the degradation or recovery state seriously. Due to such a distortion of the degradation or recovery state the MSM method
often cannot capture short-term effects because the interruption of the applied voltages might reverse their impact on device characteristics. This makes reliable short-term measurements (
1 s or
1 s) impossible.
As a result, for a long period of time models were developed based on mainly long-term measurements from
1 s to nearly 10 ks. The long-term characterization, at a first glance and in a very simplified way, shows that
in stress measurements of
large-area devices has power-law-like behavior. Thus, simple empiric models based on a power-law-like life-time estimation as shown in Figure 2.6 have been popular [32, 34–36].
The power-law covers a stress bias dependent pre-factor, a temperature dependence following an Arrhenius’ law and the power-law in time. Based on this, the can be extrapolated in order
to estimate the parameter shift over time. However, such an empirical description is quite inaccurate and overestimates the
over time because it neither
describes the short-term behavior for stress times below 1 s nor the very long-term behavior for stress times larger than 10 ks nor recovery effects due to interruptions of the stress properly as discussed in the
following.
Beside the empirically found power-law as an attempt to estimate the life-time of a transistor, also physics-based models have been introduced in order to describe the processes leading to device degradation. A widely accepted
model in this regard is the reaction-diffusion model. This model is capable of reproducing the time evolution of device degradation of large-area MOSFETs. It was introduced in 1977 [30] and
continuously adapted [32, 37, 38]. The basic assumption of the reaction-diffusion model is that -
bonds at the interface between the substrate and the oxide can be broken by NBTI stress, schematically shown in Figure 2.7. Consequently, the remaining
dangling bonds (interface-states or interface-traps) are positively charged, which can be
expressed by a interface-charge density (
), and the hydrogen atom diffuses into
the dielectric where also other
related species can be created like for example a
molecule. Further,
can also recombine with the positively charged Si dangling bond, thus the bond is again
passivated.
Figure 2.7: Schematic illustration of the classical reaction-diffusion model of NBTI: -
bonds at the interface between the substrate and the oxide are broken during NBTI stress. Neutral
, expressed by the
density
, diffuses into the oxide and leaves behind posi-
tively charged interface states.
diffusion proceeds via shallow hopping sites in the oxide shown as a regular network of
potential wells. Figure source: [31].
As soon as experimental characterization methods were improved and capable of measuring short-term effects a few inconsistencies between the reaction-diffusion model and the experimental data arose. In the context of the
improvement of measurement methods, three aspects have to be mentioned: the characterization of the recoverable component of BTI, the continuous application of stress and the broadening of the
experimental window. As an explanation, in Subsection 2.1.1 it is mentioned that as soon as the stress bias is removed a recovery effect of is measured. As long as the
stress and recovery in MSM measurements are interrupted in order to record a transfer characteristic for the extraction of
the overall degradation and recovery
state will be different than if the stress and recovery biases are applied continuously. Therefore, innovative measurement methods have been introduced, which can obtain
without any interruptions of
stress or recovery and additionally are capable of the characterization of short-term effects. An example in this regard is the OTF method capable of obtaining the
degradation without
interruptions of the stress bias. However, realized with standard equipment the OTF has an integration time of more than 20 ms in order to achieve a statistical error of
1 mV in
[39], which is quite long in
the context of short-term measurement. Soon after the OTF method had been proposed, the fast-
and fast-
methods were introduced [31, 39, 40].
Such fast methods are based on single point measurements of
during recovery instead of
interruptions in order to record an
-
. Either
or
is measured at a point near
during the recovery phase in eMSM measurements and the corresponding
is extracted. Both will be
discussed in detail in Section 3.5. These new methods extended the
and the lower limit of the experimental window during recovery (
) to 100 µs or
even 1 µs, which allows for a proper short-term characterization of BTI recovery.
The improvement of experimental setups and the broadening of the experimental window have led to different insights into degradation mechanisms and the understanding of BTI changed. Some important inconsistencies between the reaction-diffusion model and the experimental data are:
Figure 2.8: Recovery traces of a nano-scale pMOSFET and the spectral map: Two recovery traces of a pMOSFET.
Top: Recovery proceeds step-wise due to emission events of single defects in the oxide. The symbols mark the extracted emission times and step heights which are nearly unambiguous fingerprints of each defect. Bottom:
The step heights and the emission time build the spectral map. Figure source: [41].
• A behavior of
for
1 s was found. Several investigations [31,
32, 39, 42] have led to the conclusion that not only the creation of interface states contributes to
during stress but also hole
trapping in oxide defects near the interface between substrate and oxide. It has been found that there is evidence that these processes are highly coupled, which is not possible to be explained by the reaction-diffusion model.
• Even after long stress times (1 ks)
can recover more than
60 % within the first second [43]. Since the reaction-diffusion model assumes diffusion-limited degradation, which implies also a diffusion limited relaxation, 60 % of recovery means that 60 % of the hydrogen
must diffuse back to the interface and passivate the positively charged dangling bonds within one second. This implies that the backward diffusion happens by orders of magnitude faster than the forward diffusion. This cannot be
explained by the effect of diffusion since the diffusivity of
is a material constant.
• The overall recovery is considerably slower than the degradation during stress as obtained from eMSM measurements [44], which can be understood as an asymmetry of stress and recovery. In this
context, the reaction-diffusion theory predicts a relatively short recovery phase (50 % relative recovery as soon as ). Thus, the reaction-diffusion model
is not capable to model the asymmetry.
• Recovery is a bias-dependent process (shown in Subsection 2.1.1). This is not in agreement with the reaction-diffusion model because it predicts recovery due to the
back-diffusion of neutral and as such is bias-independent.
• It has been shown that interface-states nearly do not recover in the context of MSM measurements [45]. Therefore, the reaction-model, where recovery is explained as passivation of interface-states is not suitable to model recovery.
In order to overcome some of the mentioned inconsistencies, the reaction-diffusion model has been improved over the last two decades including the attempt to describe the diffusion as a dispersive process instead of a classical, i.e., Gaussian-like, process [31, 32, 46, 47].
These improvements notwithstanding, the complicated behavior of during stress and recovery
has led to the development of the non-radiative-multiphonon (NMP) model as a different approach to explain BTI. For the development of the
NMP model two processes played a major role, the improvement of measurement setups as well as the downscaling of MOSFETs. As soon as devices were scaled to the
nanometer regime it has been recognized that the recovery of MOSFETs proceeds not continuously as shown in Figure 2.2 but step-wise as
shown in Figure 2.8 top.
Back in the 80’s, it was found that random fluctuations in the terminal currents are caused by structural defects, also called states or traps, in the bulk oxide. Such fluctuations are due to defects randomly exchanging charge carriers with the substrate [13, 48]. The corresponding noise was introduced as random telegraph noise (RTN). The study of nano-scale devices has shown that device degradation and recovery is determined by single hole capture and emission processes in pMOSFETs, respectively, which is consistent with a first-order reaction-rate but not with a diffusion-limited process [40, 49, 50]. Soon it has been proposed that single oxide defects near the interface between oxide and substrate communicate with the inversion layer in the channel by exchanging charge carriers.
Such charge carrier exchange events, also called capture and emission events, of oxide defects near the interface are a serious perturbance of the electrostatic conditions in nano-scale devices. Considering the average impact of one
capture or emission event due to the downscaled device dimensions and the inhomogeneous channel potential due to randomly placed dopants [51], such events cause step-wise measurable shifts in experiments. Therefore, each
individual defect leaves its fingerprint by the fact that it appears with a certain step height (
), a certain mean value of the capture time (
) and a certain mean value of the
emission time (
) in
traces, which depend on the
position relative to the dopants, the depth of the defect in the oxide, the gate bias and the temperature. For example, as discussed in Chapter 1, the randomly placed dopants
cause the current to flow inhomogeneously from source to drain. As soon as a defect is located right above the percolation path [52], its step height can be considerably larger than estimated from the charge-sheet approximation
[53].
Figure 2.9: Step height distribution of individual defects: (a) Typical NBTI recovery traces in nano-scale devices. Each step corre-
sponds to a single gate oxide defect discharge event. (b) The step heights plotted on complementary
cumulative distribution function (CCDF) plot. The step heights appear exponentially distributed. Figure source: [18].
In this context, based on the characterization of the step heights caused by single defects, an exponential step height distribution has been found [17, 18, 54–56] as shown in Figure 2.9. Since this distribution is based on a statistical characterization, the influence of device-to-device variation of the number of oxide defects and random dopants are considered. In detail, the probability density function (PDF) can be expressed as
with
probability density function | |
threshold voltage shift | |
mean value of the step height distribution. |
The corresponding CCDF is
The mean value of the distribution can be written as
with
elementary charge | |
oxide capacitance. |
(a) Stress: single oxide defects capture holes from the inversion layer. This process is measureable as single steps at stochastically distributed around a characteristic mean
value, which depends strongly on
. With increasing
,
decreases.
(b) Recovery: single oxide defects emit the holes to the depletion layer. This process is measureable as single steps at stochastically distributed around a characteristic mean
value, which depends strongly on
. With increasing
,
increases.
Figure 2.11: Bias dependence of the capture and emission time: Three defects enumerated with 1, 2 and 3 in an pMOSFET with
and
in the range of 100 nm are characterized during (a) stress for different
and (b) during recovery
after the same
at different
. Similar to the the mea-
surements in large-area devices (Figure 2.5) the over all
of nano-scale MOSFETs
depends on
. Figure source: [33].
From experiments with the TDDS framework on nano-scale MOSFETs, it has been found that BTI degradation and recovery can be
explained by capture and emission events of single oxide defects [16]. The TDDS framework, which will be introduced in Section 3.7 in detail,
consists of several eMSM cycles followed by a postprocessing of the recorded data. is obtained during the
recovery phase by a single point measurement of
or
near
(also known as fast-
or fast-
methods in literature [31, 39, 40]).
Figure 2.8 top shows typical recovery measurements of a nano-scale MOSFET, containing the steps of five defects enumerated with 1, 2, 3, 4 and 12. Due
to the fact that the capture and emission events are assumed to be stochastic processes, TDDS requires a number, e.g.,
, of the same stress/recovery experiments in order to capture the statistics for a
reliable characterization. The spectral map in Figure 2.8 bottom visualizes the individuality of each defect. It is built by entering
and
of each emission event into a
two-dimensional diagramm. From this, the spectral map can be obtained as the distribution of the numerical data [41].
and
are strongly bias and
temperature dependent. In this regard, the bias dependence is shown in Figure 2.11 where three defects characterized on nano-scale SiON pMOSFETs capture a hole during stress and emit it during recovery. The capture events (Subfigure 2.10a) cause an increase of the absolute value of
comparable to the
degradation of large-area devices shown in Subfigure 2.4a while the emission events (Subfigure 2.10b) cause a
decrease of
comparable to the recovery
of large-area devices shown in Subfigure 2.4b. Both, capture and emission events happen at stochastically distributed
and
, respectively.
With increasing
decreases and with increasing
increases. This leads to a
different contribution of the three shown defects to degradation and recovery of
. At
−1.4 V (blue trace in Subfigure 2.4a)
of defect 2 and 3 are larger than
the upper limit of the experimental window during stress (
), which is 1 s. Thus, only
defect 1 contributes to
. At
−1.7 V (green trace in Subfigure 2.4a)
of defect 2 is decreased and
shifted to times within the experimental window. Therefore, the capture event of defect 1 and defect 2 contribute to
. Finally at
−1.9 V and
−2.2 V also defect 3 contributes to
.
At recovery conditions, the process is quite similar. While at −0.2 V all three defects contribute to recovery, at
−1 V only defect 3 contributes to
because
of the other two defects are
higher than the upper limit of the experimental window during revery (
). Quite comparable to the
measurements in large-area devices (Figure 2.5) the evolution of
of nano-scale MOSFETs is accelerated during stress with increasing
and decelerated during recovery.
The capture and emission events are also highly affected by as shown in Figure 2.12 based on the temperature dependence of the emission events. In contrast to the discussion in Subsection 2.1.1 regarding the temperature dependence of recovery of large-area devices, which is negligible, in nano-scale devices the picture is a little more complicated. Basically, with
increasing
, both,
during stress and
during recovery decrease to lower
values. In Figure 2.12 it can be seen that
decreases with increasing
but the overall difference beween
at the lower limit of the
experimental window and
at the upper limit is
temperature independent because only the three defects can contribute to recovery.
The bias dependence of the capture and emission times leads to a crossing point of both, where and
are equal, illustrated in Figure 2.20. Around this crossing point, defects cause random exchange events as shown in Subfigure 2.14b, which is called RTN. Since the whole
and
behavior is different for each defect, at a certain
some defects might capture charge
carriers (because
), some defects might emit
previously captured charge carriers (because
) and some defects might cause an
RTN signal (because
). Finally, summing up the
contribution of the transitions of all electrically active defects to
results in what is
conventianally observed as BTI degradation and recovery.
Figure 2.13: A capture/emission time: The capture/emission time (CET) map is obtained by a variation of and
at NBTI
conditions (left). The solid lines are obtained by integrating the CET map following and the dashed lines are the permanent component not visible in the CET map
(right). The CET map summarizes the particular
and
behavior of many defects. Figure source: [16].
Such a broad distribution of the characteristic times and their bias dependence can be illustrated as a CET map shown in Figure 2.13. The idea is that
similar defects can be grouped together using a suitably defined density [57]. In order to draw such a map, the capture time is
obtained at different stress conditions while the emission time is taken at different recovery conditions. With increasing
and constant
,
decreases, while
is not affected. With increasing
and constant
,
increases, while
is not affected. The particular
behavior of
and
can be plotted as a density:
or
if it is represented on logarithmic axes.
Figure 2.13 shows how broad the distribution of the capture and emission times can be, which cannot be explained by models like SRH or the reaction-diffusion model. Thus, new perspectives were needed.
Due to several inconsistencies of the reaction-diffusion model with the experimental observations, single donor-like defects in the oxide have been taken into account as the main physical cause of NBTI. The random exchange of charge carriers between an oxide defect and the substrate, which occurs if the defect energy is approximately equal to the Fermi level, produces an RTN signal in measurements as shown in
Subfigure 2.14b. One simple modeling attempt to describe charge transfer reactions in RTN signals as capture and emission events is provided by the
two-state model illustrated in Subfigure 2.14a. Therefore, the charge state of the defect was described by either the neutral state
or the charged state
with the defect occupancy of the state
(
) being
when the defect is in state
and
otherwise [41]. The transition probabilities are obtained as a Markov process. The
probability for the transition from
to
within the next infinitesimally small time interval
is given as
with and
defect occupancies of the states |
|
time | |
rate for the transition from state |
|
infinitesimally small time interval | |
higher-order terms of |
The probability that no transitions from to
occurs is given as
If is assumed to be so small that all higher-order terms are negligible and that the defect is
currently in state
,
the
probability that
is given as
By replacing the conditional probabilities in Equation 2.6 by the rates in Equation 2.4 and Equation 2.5, rearrangement and inserting for
, the differential equation can be obtained:
This is an ordinary differential equation with the solution
with
probability that the defect is in the state |
|
transition time constant. |
This solution describes the probability of the defect being in state as an exponential transition from its inital value
to its final stationary value
.
The probability that the defect is in the other state can be calculated as
. If it is assumed that
is the neutral state and
is the charged state, the capture time
and emission time
would be the transition times
from
to
(
) and from
to
(
), respectively.
and
are stochastic variables. For the
calculation of the transition times, the initial defect state is assumed to be neutral, thus, in state
(
). In this case, the time until the
defect transits to state
is independent of the backward rate
. The probability that the defect is in
state
at a certain time (
) is given as
and that
it is in state
as
. If
, the probability that the
defect is in state
can be written as
and the PDF can be expressed as
. The mean value of
is the expectation value of the
exponential distribution, which is given by
Similar arguments hold also for the emission time:
with
mean value of the capture time |
|
probability density function. |
A proper RTN analysis is only possible if (energy level of the defect is located near the Fermi level), (
,
)
,
and
,
at certain
and
. Only RTN signals caused by defects with
characteristic times, which fullfil these prerequisites, can be characterized because of a statistically meaningful number of transitions.
If or
, eMSM measurements are required where the gate bias is switched from
to
and back to
in order to obtain the
probability transition. For this it is assumed that the Markov process is stationary before each change of the gate voltage. Before switching from
to
the probability that
the defect is in its state
is given as
. With Equation 2.8 the probability after switching the gate voltage from
to
can be calculated
as
and the probability after switching the gate voltage from to
as
with
time constant for the transition from recovery to stress / from | |
stress to recovery conditions | |
defect time constant at different gate bias | |
gate bias at stress/recovery conditions | |
stress / recovery time | |
point in time when the bias conditions are switched from | |
stress to recovery | |
occupancy. |
The corresponding transition time constants are given as
and
The corresponding occupancies are given as
and
According to Equation 2.11, the occupancy for the transition from to
is
while according to Equation 2.12, the transition from to
is
Experimentally the differences
is seen when switching from recovery to stress conditions and
when switching from stress to recovery conditions which results in
and
respectively.
The overall degradation can be obtained as
with
defect index | |
total amount of active defects | |
step height of defect |
|
Figure 2.16: Configuration coordinate diagram for a two-state model using a non-radiative multiphonon theory: The transition from to
proceeds either radiatively or non-radiatively. In typi-
cal semiconductor devices, the radiative transition can be excluded as no photons are available during the regular operation. Therefore, the energy needed to overcome the difference between the minimum point and the crossing point
of the parabolas hasto be supplied by phonons. Figure source: [58].
So far, the stochastic process of capture and emission events has been formulated based on a two-state model. In order to be able to calculate the transition rates between the state and
, it has to be considered that when electrons or holes
are captured or emitted from oxide defects the whole surrounding (electrons and nuclei) is influenced. In each state, neutral and charged, the total energy consists of contributions from the ionic system, the electronic system, and a
coupling term. In a simplified way, the atomic positions are reduced to one-dimensional configuration coordinates and the adiabatic energy surface, which would be obtained by solving the Schrödinger equation, is approximated by a
harmonic oscillator. The total energy of each charge state
can be written as
with
total energy of the charge state |
|
effective mass | |
reaction coordinate | |
local equilibrium position | |
vibrational frequency in minimum |
|
potential energy. |
This parabolic approximation is shown in the configuration coordinate diagram in Figure 2.16 for both states and
. For the calculation of the transition rates of such a
defect, two transition possibilities between the neutral and the charged state can be considered as shown in Figure 2.16, the radiative transition and the non-radiative
transition. The radiative, or optical, transition occurs around the minima of the parabolas according to the Franck-Condon principle. During the transition from state
to state
the lattice coordinate
does not change and a photon would have to supply
the energy to the system. However, no photons are available for such direct transitions during regular operation in typical semiconductor devices. Therefore, the transition between
and
has been described by non-radiative multiphonon processes [13–15], where the energy
to overcome the barrier has to be supplied by phonons. This means that the system has to overcome the difference between the minimum points
or
and the crossing point of the parabolas
as illustrated in
Figure 2.17.
The NMP transition describes the charge carrier transfer between the conduction or the valence band of a semiconductor and the oxide trap. The corresponding rates for continuously distributed charge carrier energies can be written as [59, 60]
with
transition rate from |
|
transition rate from |
|
energy | |
trap level | |
conduction / valence band edge energy | |
density of states of the conduction / valence band | |
carrier distribution functions for electrons / holes | |
electron wave functions of both states and accounts | |
for possible tunneling processes | |
lineshape function |
Under homogeneous bias conditions the carriers in the channel are in equilibrium and thus the carrier distribution functions, and
, are properly described by the
Fermi-Dirac distribution. Substituting
and
by the Fermi-Dirac distribution and
considering a linear electron-phonon coupling, the transition time constants for hole capture and emission are given by
with
minimum of the total energy of the charge state |
|
energy barrier height for the transitions |
|
difference between |
|
parabolas (Figure 2.17) | |
Boltzmann constant | |
temperature. |
(a) The energy level of the defect at the depth
is located below or above the Fermi level if recovery conditions
or stress conditions
are applied, respectively.
(b) The active energy region (AER) defines the region where energy levels of defects may be located in order to be shifted above the Fermi level when a stress bias is applied and below the Fermi level when a recovery bias is applied.
Figure 2.19: Region of defects actively contributing to the degradation and recovery in an NBTI setting: Defects whose energy levels are located in the AER are neutral prior stress, can be potentially charged during stress and discharged again during recovery. Furthermore, the defect energy band is chosen in such a way that the contribution of defects located in right half of the oxide dominates the degradation. Figure source: [16].
The relative position of the parabolas depends on , which leads to a field- and
temperature-dependence of the NMP transition as shown in Figure 2.17. At recovery conditions, the minimum of the neutral state parabola
is located energetically below the
minimum of the charged state parabola
. If the defect was previously charged, it
will transit from the charged state to the neutral state. At stress conditions,
and a previously
neutral state will transit to the charged state. According to Equations 2.9 and 2.10, the field- and temperature-dependence of the
transitions rates leads to a field- and temperature-dependence of
and
, which reflects the experimentally
observed behavior of single oxide defects discussed in Subsection 2.1.3.
Figure 2.17 already illustrates that in eMSM measurements only defects in a certain energy region contribute to . This area is the AER and is shown in Figure 2.19 [16]. As an explanation, a defect energy level
, which is below the Fermi level
at recovery conditions (low level is
abbreviated with L,
) and above the Fermi level at stress
conditions typically above nominal operating conditions (high level is abbreviated with H) is withing the AER. Following the switch from the recovery to the stress voltage, defects with energy levels
within the AER are moved above the Fermi level and capture charge carriers. Therefore, as time progresses, the AER determines the maximum possible degradation.
Back at recovery voltage, the defects are moved back below the Fermi level and emit the charge carriers again.
The boundaries of the AER can be defined as shown in the following. depends on the bias via the
depth-dependent electrostatic potential
:
.
At low defect concentration, it can be assumed to first-order that the charged defects inside the oxide do not significantly impact the electrostatic potential. With this assumption, the potential can be written as
where is the potential at the interface.
In a simple approximation, the trap level depends on the applied bias via
With this, the lower boundary () of the AER can be written as Equation 2.27 and the upper boundary (
) of the AER can be written as Equation 2.28
with
lower / upper energy boundary | |
elementary charge | |
potential at the interface at stress / recovery conditions | |
electric field across the oxide at stress / recovery conditions | |
depth |
Although the two-state model can explain a field- and temperature-dependence of the characteristic capture and emission times, important details seen in experiments are still missing in this model. For example:
• The predicted field-dependence of is nearly linear, which is not the case in experiments.
TDDS data shown in Figure 2.20 illustrates that
shows some curvature on a logarithmic scale.
• Defects have been observed which show an interrupted RTN signal [40, 41, 62]. Figure 2.21 illustrates a defect, which produces an RTN signal only for a limited amount of time after NBTI stress. Such observations have led to the conclusion that in addition to a neutral and a charged state also a metastable state must exist. This metastable state can either be neutral or charged.
• cannot be explained properly by a two-state model.
As shown in Figure 2.20 two types of defects occur, which have been named switching and fixed oxide defects [61]. In the first case
is nearly constant and shows only a slight
bias-dependence. In the second case
is nearly bias-independent above
and drops below
. Such a behavior could be captured
by two different paths for the emission process.
Especially the last two findings have led to the consideration of additional states. As a result, the four-state NMP model has been proposed [40].
In order to reflect experimental observations like different behavior and interrupted RTN signals, the two-state model has been extended as shown in the diagram in Figure 2.22 [16]. The potential energy surface is illustrated in
Figure 2.23. The resulting four-state model consists of the two stable states
(neutral) and
(charged), which correspond to the two states in the two-state model, and additionally
two meta-stable states,
(neutral) and
(charged). The transitions between
and
and vice versa as well as
and
correspond to NMP transitions as discussed in
the previous subsection. The transitions from
to
and vice versa as well as from
to
proceed via a thermal barrier. This thermal barrier is associated with a structural
relaxation of the defect and is described by transition state theory [63, 64] as
with
transition rate |
|
attempt frequency, | |
energy barrier height, | |
Boltzmann constant, | |
temperature. |
Assuming the defect is in its neutral state , the capturing of a charge carrier proceeds via
. The NMP
transition
reflects the charging of the defect and corresponds to what is
experimentally measurable. This transition is followed by a transition to the stable state
via the thermal barrier.
The emission process may proceed via two different paths, either (fixed oxide traps defects) or
(switching oxide defects). Figure 2.23 shows the case of a switching defect. If the defect is in the stable and charged state
, the transition to the metastable state
is an NMP transition, which is followed by a
thermal transition to the stable state
. The experimentally measurable
step in a recovery trace
corresponds to the transitions
and
.
The NMP transition rates can be calculated using the Equations 2.21 to 2.24:
The four-state model can be written in a similar manner to the one of the two-state model. As a result, the overall capture and emission times (transition from one stable state to the other via a meta-stable state) can be written as
and
respectively where corresponds to
and
to
.
The four-state model captures the bias- and temperature-dependence of the capture and emission times quite well. It can also explain the interruption of RTN signals, where the RTN is, for example, the hopping between and
and the interruption is the transition to the stable state
.
However, at this point the question which structural oxide defect would cause measurable steps in the traces remains open.
Promising defect candidates suitable for the four-state model are the oxygen vacancy and the hydrogen bridge defects [66, 67]. Moreover, the hydroxyl-
center has also been proposed as a possible defect candidate [65].
The atomic configurations of all three defect candidates are shown in Figure 2.24. However, by a statistical analysis of the experimentally found NMP parameter distributions (shown in Figure 2.23) for numerous defects and comparison with the parameters extracted from density-functional-theory (DFT) calculations [68] show that the oxygen vacancy is a very unlikely defect candidate [65]. By contrast, the hydrogen bridge and the hydroxyl-
give a good match for the majority of the parameters of the
four-state model. Therefore, both of them are promising defect candidates for the four-state model.
Figure 2.24: Possible defect candidates: Atomic configurations corresponding to the states ,
,
and
for three possible oxide defects [65]. Top: Oxygen vacancy. Center:
Hydrogen bridge. Bottom: Hydroxyl-
center. H atoms are shown as silver, Si atoms are yellow and O
atoms are red. The blue bubbles represent the localized highest occupied orbitals for the neutral charge states and the lowest unoccupied orbital for the positive charge states. Figure source: [65].
Although the extension of the two-state model to a four-state model reflects the experimental observations quite well, the whole picture is still not completed. As will be discussed in the following, observations like the permanent component and volatility of defects need for further extensions.
The four-state model, as discussed so far, has been developed for active defects, which basically can be characterized in TDDS measurements ( and
,
for any
,
and
). However, it has been found that oxide defects can all of a sudden disappear from one
to the other measurement from the measurement window (
,
and
,
) as it is shown in Figure 2.25 based on spectral maps for four different TDDS measurements. Additionally, the disappeared defects can also reappear. An electrically active
state can be modeled using the previously discussed four-state NMP model. The disappearing of a defect in TDDS measurements can be described as a transition from
one of the four states to an inactive state. This transition from an active state to the inactive state as well as the backward transition have been formulated as volatility [65, 67, 69, 70].
As it is shown in Figure 2.26 the dis- and reappearing can occur several times during TDDS measurements. The corresponding time constant for the transition from the active into the inactive state is typically in the range of hours to weeks. It has been proposed that the transitions between active and inactive states can be described as thermally activated rearrangement of the atomic structure. The reaction barrier can be estimated as [65, 70]
with
transition time constant for volatile transitions | |
attempt frequency | |
energy barrier height. |
The possible potential energy surface of this thermal transition into an inactive state is shown in Figure 2.27 and the corresponding atomic structure on the right
hand side of Figure 2.30. Both figures show the transition of a hydroxyl-
center, where
is the charged metastable state of the four-state model. As a general
explanation, for the atomic structure the transition from activity to inactivity means that a hydrogen atom is released from the hydrogen bridge or the hydroxyl-
center and relocated to a neighboring atom. This corresponds to
either a neutral
atom moving away from the neutral defect state, which is associated with a transition to
the neutral volatile state
, or to a proton from the positive defect state, which is associated with a
transition to a positive volatile state
. This results in four possible purely thermally activated transitions starting from a
four-state model:
,
,
and
. From these four, it has been found that the
transitions starting from
and
are always lower in energy [70], especially
is a quite promising transition for the explanation of
volatility. Moreover, it has been found that the hydrogen bridge is not a suitable candidate to explain volatility since the transition barriers are too high to explain the experimental characterizations. By contrast, the hydroxyl-
center has been considered as the suitable defect candidate for the
explanation of volatility.
Figure 2.27: Example of the potential energy surface of a hydroxyl- center including volatile states: The defect can become volatile
starting from a positive charge state, which is one of the four (active) NMP states. As soon as it overcomes the barrier
it is inactive and not visible
in measurements. Figure source: [65].
Figure 2.27 shows the hydroxyl- potential energy surface of the extension of the four-state model
based the transition
. As discussed in the previous paragraph, two additional
states, a positive
and a neutral
and their respective barriers are added. Theoretically, in such a
configuration, it would be possible that transitions between
and
cause RTN since they include a hole
capture or emission. However, this has been discarded because it has been shown that due to typical transition barrier heights
,
and
charge capture or emission events in the
volatile states would occur most probably with a similar or lower frequency as volatility itself [58].
Basically, transitions from other active states are also possible, for example, the transition via a hydrogen hopping process. However, it has
been found that this transition is associated with the permanent component of degradation as will be discussed in the next subsection.
Oxide defects contribute differently to during recovery and thus can
be classified into defects contributing to the recoverable component and defects contributing to the permanent component of degradation [71, 72]. Those with characteristic capture and emission times lying within the measurement
window are typically associated with the recoverable component while those with
but slowly-relaxing,
, are associated with the
permanent component. However, properties like
and
and thus their assignment to the
recoverable or the permanent component is highly alterable due to reactions with hydrogen [69]. Defects can also be created or annealed, whereby these terms are often related to the transition from the active to inactive states or to
precursor states [62, 65, 69, 72]. The particular properties and their contribution to degradation can be spread widely.
In order to explain the permanent component of in NBTI measurements a gate-side hydrogen release model has been proposed [73, 74]. The idea is based on the fact that in amorphous
hydrogen can bind to a bridging oxygen, as
calculated in recent DFT calculations [75, 76]. Throughout the binding process, the hydrogen can release its electron and bind to the oxygen or the hydrogen breaks one of the
-
bonds and forms a hydroxyl group, which faces the dangling bond of the other
. Such a defect is quite similar to the
center and is additionally to the previously discussed defects a
proper candidate for the explanation of volatility.
A schematic illustration of the hydrogen release model is shown in Figure 2.28. During stress, the energy level of a trapped near the gate can move below the Fermi level. Consequently, it is neutralized and
emitted over a thermal barrier. The
moves quickly towards the channel where it can become trapped in a
preexisting hydrogen trapping site, again releases an electron and causes a
shift. The gate side can be
interpreted as a hydrogen reservoir.
Figure 2.28: Schematic Hydrogen release mechanism: At the gate side a proton is trapped. During stress, the trap level can be shifted below the Fermi level, which makes
it possible for the proton to be neutralized. This neutrally charged hydrogen atom can now be released by overcoming a barrier and move towards the channel side. The empty trap site can potentially be refilled by released from the gate. This process should be strongly temperature dependent. Figure
source: [74].
Figure 2.29 shows schematically that the hydrogen release model can be formulated by assuming that the oxide consists of discrete interstitial sites at which hydrogen can occur in a neutral position. From this interstitial sites, it can
be either trapped in a neutral configuration or in a positive configuration. The rate equation for the interstitial hydrogen species can be written as
with
expectation value of hydrogen in a neutral interstitial | |
position at site |
|
time | |
hopping rate from interstitial site |
|
thermal transition | |
defect site where the hydrogen can be trapped | |
neighbouring sites | |
trapping rates for interstitial site |
|
with several trapping sites |
Thereby, one spatial interstitial site is allowed to interact with several trapping sites
. The corresponding trapping rate is
with
transition rate from the interstitial to the neutral | |
trapped configuration / from the neutral to the | |
interstitial, thermal transition | |
maximum number of trapped hydrogen atoms | |
expectation value of trapped neutral / positive | |
hydrogen trapped. |
The temporal change in the number of neutral and positive trapped hydrogen atoms is given by
with
transition rate from the interstitial to the neutral | |
trapped configuration / from the neutral to the | |
interstitial, thermal transition. |
Figure 2.29: One dimensional schematic of the H-release model: The oxide of a MOSFET consists of potential trapping sites for hydrogen. Hydrogen
can either occur in a neutral interstitial position (grey) or as a trapped neutral configuration (blue) or in a trapped positive configuration
(red). The gate side acts as an additional hydrogen reservoir. Due to the high diffu-
sivity of hydrogen the exchange to a new trapping site can ocur very fast and is therefore not rate limiting. Figure source: [74].
The trapping rates describe the transition from the interstitial to
the neutral trapped configuration. The corresponding transition rates
and backwards
are modeled as a thermal activation
using an Arrhenius law for each trapping site
. The number of neutral and positive trapped
hydrogen can be calculated using rates with standard non-radiative multiphonon theory.
Figure 2.30: Extended four-state NMP model: Illustrated for a promising defect candidate, the hydroxyl- center. Still, the core of this model (middle) is build around the
bistable defect with four states (
,
,
,
) and describes the active defect, which is capable of capturing and emitting
charge carriers. However, the extended variant of the model also accounts for the inactive phases of the defect via transitions to the precursor states
and
(left) and the inactive states
and
(right).
Figure 2.30 shows a complete picture of all defect states being capable to describe the recoverable and the permanent component of NBTI degradation as well as the temporary inactivity of single oxide defects. This extended four-state model includes the four active states (center), the transition to the inactive states starting at state (right) and the transition to the precursor states starting at state
(left) of a hydroxyl-
center.
In Chapter 1 it is mentioned that basically two types of defects appear in MOSFETs, the interface defects and the oxide defects. So far, it
has been discussed how charge carrier exchange between oxide defects and their surrounding affect the device parameters in the context of NBTI degradation. In this chapter, the most important
modeling approaches for the degradation mechanism HCD, which is associated with the creation of interface defects, are summarized. Similar to BTI, also HCD is a detrimental mechanism in MOSFETs, which affects device parameters, such as ,
and on-resistance (
). In this context, hot is
associated with the kinetic energy of the carriers accelerated by high channel electric fields. Therefore, HCD is best observed at high electric fields along the channel, which is typically achieved by a
high drain voltage at stress conditions (
) and a gate bias close
to the operating conditions.
The process itself is known since the 60’s [77] and over the time several modeling approaches have been made in order to reflect the changing impact on MOSFET parameters because of the scaling
trend. In this context, several attempts have been made in order to distinguish different HCD modes [78], e.g., hot-carrier injection (HCI). HCI is associated with channel carriers, which are entering the conduction band of the oxide as they overcome the energetic barrier between the substrate and the oxide. This requires a kinetic energy higher
than eV. Although the electric fields in the device increased due to the scaling of
device dimensions, the simultaneous reduction of the operating voltages compensated this increase and led to a lower kinetic energy of the carriers. Therefore, HCI has faded from the spotlight and new
modeling attempts have been made.
One of the first successful HCD models was the so-called “lucky-electron" model [79], valid for long channels or high electric fields. This concept introduces a threshold energy level which needs to be surmounted by the carriers in order to trigger impact-ionization. As soon as a carrier travels a sufficiently long distance without collisions, this energy can be reached. However, it has been found that even for low operating voltages around 1.5 V in devices with dimensions in the deca-nanometer regime HCD is a severe degradation mechanism [80, 81]. Thus, models were required, which take into account colder carriers as a physical cause for HCD.
HCD in experiments is often characterized by either using the charge pumping method (Section 3.2) in order to extract the number of interface states or
by measurements of the linear drain current shift (). Since defects located at
the oxide/substrate interface cause surface scattering, which lowers the carrier mobility and tilts the transfer characteristics, the impact of HCD is much more pronounced in
than in
.
can be measured using the method
for
extraction discussed in
Subsection 2.1.1. The stress and recovery phases are interrupted periodically in order to record an
-
characteristics, extract
and subtract it from the unstressed
value. In contrast to BTI and as already mentioned in Subsection 2.1.2 created interface states barely recover. Therefore, the recovery of HCD is negligible, and interruptions of the stress conditions hardly affect the degradation state of
.
The temperature dependence of HCD is different than the one of BTI. For long channel devices, for example, the degradation of is less detrimental at increased
temperatures. However, for short-channel devices HCD is accelerated at higher temperatures [82]. This channel length and temperature dependent acceleration of degradation is caused by
temperature-dependent contributions of scattering effects, which may populate the high energetical fraction of the carrier ensemble [23].
In contrast to the temperature dependence of HCD, the field dependence is independent of the channel length. In general, the degradation of is highly channel electric field
dependent [23, 83]. However, investigations have revealed that the peak of the electric field, the peak of the average carrier kinetic energy and the maximum of the created interface defect density do not correlate with each other
[84–86].
The Hess model proposes that HCD is determined by the dissociation of neutral hydrogen-passivated dangling bonds at the substrate/oxide interface by channel carriers (see
Figure 2.31) [87–90]. This is based on two ideas: a hot carrier with sufficient kinetic energy scatters with a dangling bond and causes it to break (single particle process,
shown in the left panel of Figure 2.32), as well as multiple colder carriers cause one bond to dissociate (multiple particle process, shown in the right panel of
Figure 2.32). The bond breakage process at the interface between substrate and oxide results in
centers [91, 92], which can
capture and emit charge carriers and distort device characteristics. For example, the trapped charges act as Coulomb scattering centers and degrade the carrier mobility. The capture and emission dynamics are described by the
standard SRH theory.
Figure 2.32: Single-particle and multiple-particle mechanism: A schematic representation of the SP- and MP-mechanisms. According to the SP-process a solitary energet- ical carrier can dissociate the bond. The MP-mechanism corresponds to the subsequent bombardment of the the bond by several colder carriers followed by the bond excitation and eventually the H release. Figure source: [23].
For the modeling of bond dissociation, the Si-H bond is typically modeled using a truncated harmonic oscillator [23]. This oscillator is characterized by the system of eigenstates as shown in Figure 2.33. The single particle process corresponds to the excitation from one of the eigenstates to the last bonded state and the transition to the transport state. Most probably, the interaction
energy excites the bonding electron of to an antibonding state, which consequently leads to the release of the hydrogen atom.
The desorption rate of this process can be written as the acceleration integral [90]
with
desorption rate for the single particle process | |
threshold energy | |
carrier impact frequency on the surface per unit | |
area within the range of |
|
desorption probability | |
energy-dependent reaction cross section. |
The multiple particle process corresponds to an excitation from one eigenstate to the next with each scattering process between a colder carrier and the Si-H bond, whereby the occupation number obeys a Bose-Einstein distribution. This multivibrational mode excitation is accompanied by the phonon mode decay with the corresponding rates
with
total phonon emission / absorption rate | |
Threshold energy | |
carrier impact frequency on the surface (per unit | |
energy and area), | |
scattering cross-sections for bond-phonon | |
emission / absorption | |
phonon occupation numbers | |
phonon energy. |
The bond rupture happens from the last bonded level to the transport state. Finally, the bond-breakage rate corresponding to the multiple particle process can be written as
with
bond-breakage rate corresponding to the multiple particle process | |
energy of the last bonded level in the quantum well, dissociation energy | |
phonon energy | |
Boltzmann constant | |
lattice temperature | |
total phonon emission / absorption rate | |
phonon reciprocal life-time. |
The Hess model was quite revolutionary because it expressed the idea that HCD is controlled by the distribution function, which enters the acceleration integral in Equation 2.40. It consideres the interface traps on a microscopic level. However, it remains unconnected to the device level. For example, the degradation of parameters like and
cannot be modeled with the Hess
model only.
Rauch and LaRosa suggested an alternative empirical model, which reflects the importance of the carrier energy on the degradation. The so-called energy driven paradigm consideres that in the case of scaled devices with channel lengths less than 180 nm the driving force of HCD is the carrier rather than the electric field [24, 83, 94, 95] as it was in the “lucky-electron" model. One further issue associated with the approach of Rauch and LaRosa is the increasing impact of the electron-electron scattering on HCD at reduced channel lengths because it populates the high energy tail of the carrier distribution function.
The impact ionization rate as well as the rate of hot-carrier induced interface state generation is controlled by terms as the following.
is the carrier distribution function and
is the reaction cross section. While the first
is strongly decaying with increasing energy, the second one grows power-law-likely. The product of both results in a maximum. As long as this is sufficiently narrow, it can be approximated by a delta-function, which avoids
time-consuming calculations of the carrier distribution function. The integral can be substituted by a stress condition related empirical factor.
Although the findings of Rauch and LaRosa are a substantial simplification of the HCD treatment, the energy driven paradigm suffers from some shortcomings. For example, the product is not necessarily narrow. Moreover,
the energy driven paradigm does not consider
as a distributed quantity and,
therefore, it does not capture the strong localization of HCD.
The Braivaix model is based on features of both, the Hess model and the findings of Rauch and LaRosa. Important ideas of the Hess model which enter the Bravaix model are the interplay between single and multiple carrier
mechanisms as well as the realization that the damage is defined by the carrier distribution function. The latter enters Equation 2.43 via the particle flux in
and
. The findings of Rauch and LaRosa enter
the Bravaix model via the substitution of the acceleration integral by the stress condition related empirical factor discussed in the previous subsection.
The Bravaix model describes the kinetics of the oscillator (Figure 2.33) as a system of rate equations [22, 90, 96]:
with
occupancy of the |
|
time | |
total phonon emission / absorption rate | |
last bonded level | |
rate of hydrogen released to the transport state, thermal barrier | |
interface-charge density | |
concentration of the mobile hydrogen |
The phonon emission and absorbtion rate are calculated differently to Equations 2.41 and 2.42 [90]:
with
total phonon emission / absorption rate | |
drain current density | |
cross-section of excitation of a phonon mode | |
phonon life-time | |
phonon energy | |
Boltzmann constant | |
lattice temperature | |
Based on the energy-driven paradigm the integral can be substituted by the empirical factor . With this and for the case of weak
bond-breakage rate the equation system 2.44 to 2.46 can be solved for
to yield:
The multiple particle process related interface state generation rate (bond-breakage rate corresponding to the multiple particle process) can be written as
with
ground state, it is assumed that the bond occurs most likely in the | |
ground state |
|
energy of the last bonded level in the quantum well, dissociation energy | |
empirical factor substituting the acceleration factor (energy-driven | |
paradigm) | |
drain current | |
thermal energy barrier of hydrogen released to the transport state | |
phonon energy | |
Boltzmann constant | |
lattice temperature | |
phonon reciprocal life-time. |
Depending on whether the stretching or bending vibrational mode is considered, the values for ,
and
can be chosen [96]. With the
findings of all involved persons, the dissociation rate by multiple particle processes is represented quite well. Consequently, the life-time can be estimated for the different regimes like the hot-carrier regime where the single particle
mechanism plays the dominant role, the intermediate case where electron-electron scattering leads to a population of the high energetical tail of the charge carriers and the high electron flux where the multiple particle process
dominates the bond dissociation.
Nevertheless, the missing carrier transport treatment which allows one to distinguish between the single particle process, electron-electron scattering, and multiple particle process driven modes, affects the model quality. Since these mechanisms affect each other via the carrier distribution function they have to be considered. Moreover, the scheme for the single particle process rate is based on fitting parameters and not on physical mechanisms.
In order to overcome the disadvantages of the Braivaix model, a model based on the exact solution of the Boltzmann transport equation (BTE) has been proposed [23, 93, 97, 98]. This approach captures the physical picture behind HCD more accurately by covering three aspects of HCD: the carrier transport, a microscopic description of the defect creation kinetics and the degraded device simulation. The aspect of the carrier transport is solved by using either a stochastic or a deterministic solver of the BTE. While the stochastic solver employs the Monte Carlo method, the deterministic solver is based on the expansion of the carrier density function in a series of spherical harmonics. The latter appears especially for ultra-scaled devices more appropriate because electron-electron scattering, for example, can be implemented easily without leading to a long computational time.
Furthermore, for a proper HCD treatment one has to consider both types of carriers, minority and majority. Due to impact ionization (II),
secondary majority carriers are generated. If the device is operated near or beyond pinch-off conditions, channel carriers with sufficient kinetic energy can trigger impact ionization, thereby, generate secondary majority carriers which
are accelerated towards the source due to the channel electric field. As a consequence, additional interface states to those created by the primary channel carriers can be created and result in an additional peak of the interface state
density shifted towards the source (see
Figure 2.34). This additionally created interface states significantly change the degradation characteristics [99, 100].
Figure 2.34: Evolution of lateral trap density distribution with stress time: and bulk-oxide-
charge density (
) as a function of the lateral position at
different stress times. It is clearly visible that a second
peak occurs due to interface states cre-
ated by secondary generated majority carriers. Figure source: [101].
For a proper modeling approach, the distribution functions for both, majority and minority charge carriers, are evaluated at each point at the interface. The distribution functions enter the carrier acceleration integral, which controls single particle as well as multiple particle mechanisms.
with
carrier acceleration integral | |
threshold energy | |
carrier distribution function | |
density-of-states | |
reaction cross section | |
carrier velocity |
For the single particle process, the superposition of electron and hole acceleration integrals weighted with the corresponding attempt frequencies gives the generation rate (bond-breakage rate corresponding to the single particle process)
with
ground state | |
attempt frequencies for electrons / holes | |
acceleration integral for electrons / holes | |
time |
For the multiple particle process, the -
bond is treated as a truncated harmonic oscillator, which leads to the bond-breakage
rate corresponding to the multiple particle process
with
ground state | |
last bonded level | |
rate of hydrogen released to the transport state, thermal barrier | |
rate of passivation of dangling bonds | |
total phonon emission / absorption rate | |
time. |
The model is able to capture the degradation of MOSFET parameters like measured in devices with different
channel lengths and at different hot-carrier (HC) stress conditions. As will be shown in Chapter 5, also effects associated with
oxide defects can be explained. In particular, with a thorough carrier transport treatment and under consideration of secondary generated majority carriers in the channel also recovery after different stress conditions can be modeled
properly. However, one open question remains, namely how oxide traps contribute to HCD. As already shown in Figure 2.34, not only
but also
increases with the stress time. It has
been assumed that so-called turn-around effects shown in Figure 2.35 could be the result of the interplay between different defect types [23].
Stress time-dependent turn-arounds of degradation as shown in Figure 2.35 have been discussed in literature for and
[99, 100, 102]. A
turn-around means in this regard that the degradation trend changes after a certain stress time. In Figure 2.35,
initially decreases while after
10ks it starts to increase.
In the case of degradation, it has been proposed
that the turn-around can be explained by two aspects. The first aspect concerns the additionally created interface states by secondary generated carriers as already mentioned in the previous subsection. The second aspect, which is
finally responsible for the turn-around itself, is the interplay between
contributions of defects at
the interface and the oxide [101]. In case of
degradation, it has been
demonstrated that during stress
decreases due to minority charge
carriers trapping in the oxide while after a certain stress time it increases due to trapping of majority charge carriers by interface traps, generated during stress. This turn-around effect is caused by the partial compensation of the
charge stored in the oxide traps by interface state trapping.
The explanation for the turn-around in is quite similar to the one
for the turn-around of
. Charges of opposite signs
are trapped in different sections of the characterized transistor [102]. As a result,
first increases followed by a
decrease for longer stress times. In Section 5.1 it will be shown that a turn-around effect was measured. However, the exact interplay between oxide defects and interface defects
remains still an open question.
Typically BTI and HCD are discussed and characterized independently from each other with regard to defect creation and annealing, the permanent and recoverable
component, and their impact on parameter shifts. Although MOSFETs are not only subjected to either BTI or HCD conditions but also
to stress conditions where both mechanisms contribute to degradation, only a limited number of studies is available on their simultaneous contribution or their interplay [21, 25–27, 103]. In this context, the term of mixed BTI/HC stress is used in order to express conditions linked to
0 V and
0 V.
So far, oxide defects in the context of BTI where is zero during stress have been
discussed. In such a case,
could be approximated as laterally
homogenous, which means that it has the same value for each lateral defect position (
). The behavior of oxide traps depend on
the defect properties, which are reflected in the NMP rates. Their contribution to degradation and recovery is given typically by characteristic times, which fulfill the following requirements:
and
,
. In this subsection the impact of
0 V on the contribution of oxide
defects to degradation and recovery is discussed.
In the case of a pMOSFET, as soon as both, and
, are less than zero, the lateral
dependence of the channel potential (
) has to be considered. In the simplest
case,
can be approximated linearly [27]
for those positions where the condition of inversion is fulfilled. At the pinch-off point it can be written as
with
channel potential | |
drain voltage | |
gate voltage | |
absolute lateral position (0 at source and |
|
channel length | |
threshold voltage. |
Since the applied is constant over all lateral positions, but
the channel potential increases from source to drain,
, which is proportional to the difference
of both, will decrease from source to drain. As
remains unaffected at the source-side
compared to homogeneous NBTI conditions, but is reduced at the drain end of the channel, different lateral positions will contribute differently to degradation and recovery. In a very simplified model
based on an exponential dependence of the degradation on the applied gate to channel voltage, a lateral position dependent
can be expressed as
Figure 2.36: Contribution of active oxide defects at different stress conditions shown for a pMOSFET: Schematic illustration of eight uniformly
distributed oxide defects. Top: At homogneous NBTI stress conditions (left) all defects capture a hole, each shown as filled circles and emit at recovery conditions (right), shown as empty
circles. Therefore, all defects contribute to the recoverable component. Bottom: At inhomoneous NBTI stress or in more general mixed stress conditions where
and
(left) three defects near
the source capture a hole each, illustrated as filled circles, two defects in the center capture a hole each but with a reduced occupancy, shown as light red filled circles and three defects near the drain do not capture a hole at all, shown
as empty circles. At recover conditions (right) only defects which have captured a hole during stress – something in between of three and five – emit. Therefore, only three to five defects contribute to the recoverable component instead
of eight.
with
position dependent threshold voltage shift | |
stress time and temperature dependent constant | |
absolute lateral position (0 at source and |
|
stress time | |
technology dependent constant | |
channel potential. |
Equation 2.56 shows that while each lateral position contributes equally to for homogeneous NBTI, at inhomogenous NBTI conditions with
0 V and
0 V each position contributes
differently. This means that positions within the region near the source, where
is very low, contribute more to
than positions within the
region near the drain, where
might even reduce
to zero. From the perspective of
degradation being the result of capture events of oxide defects, Figure 2.36 shows schematically what would happen from an electrostatic point of view. It is assumed that the
shown eight defects, uniformly distributed over all lateral positions, contribute to degradation and recovery at NBTI conditions by capturing a hole during stress and emitting it during recovery. This
means that the energy levels of the defects are below the Fermi level at recovery conditions, and at each position
is sufficient to shift the energy levels
above the Fermi level during stress. In other words all shown defects are within the active energy region and
as well as
,
. By contrast, in the case of inhomogenous NBTI conditions,
remains quite unaffected in the region
near the source but is seriously reduced in the region near the drain. As a result, the energy level of source-side defects can be shifted above the Fermi level during stress, thus such defects can capture a hole during stress and emit it
during recovery. Quite to the contrary, the energy level of some drain-side defects can no longer be shifted above the Fermi level during stress, thus, the drain-side defects do not capture a hole. Defects in the central region most
probably will show a reduced occupancy.
In Figure 2.36 it it can be seen that not only the contribution of oxide defects to the total degradation changes at inhomogneous NBTI
conditions compared to homogenous NBTI conditions but also their contribution to recovery. In this context, after homogeneous NBTI stress all eight defects emit a hole
during recovery but only three to five defects emit one after inhomogenous NBTI stress. Thus, recovery will be reduced with increasing .
In such a simplified electrostatic picture, the significant change of the behavior of drain-side defects is attributed to the dependence of the characteristic
capture and emission times (Equation 2.25 and Equation 2.26) and of the occupancy (Equation 2.17 and Equation 2.18). At the defect level a reduction of
typically leads to an increase of
, a decrease of
and a decrease of the occupancy.
Therefore, at inhomogeneous NBTI stress conditions, the transition constants of source-side defects remain nearly unmodified while those of drain-side defects are significantly modified. In other words,
the active energy region narrows from source to drain as shown in Figure 2.37. As a consequence, independently of the total number of defects, those at the drain-side will
contribute less to degradation and recovery than those in the central region or at the source-side.
As will be discussed in Chapter 5, the whole picture is more complicated since effects like II have to be taken into account as well. As a main result of this thesis, it will be shown that taking only the modified electrostatics during mixed NBTI/HC stress into accound does not reflect the defect behavior in experiments fully.
The drain voltage has not only a considerable impact on the defect behavior during stress as shown in the previous section but also on the behavior during recovery. It has been shown that the exponential step height distribution
introduced in Equation 2.2 depends on the readout conditions [17]. A typical drain voltage at recovery conditions () is −0.1 V
(for pMOSFETs) and the gate voltage
. Similar to what has been discussed
in the previous subsection, the lateral local electrostatic conditions change when
−0.1 V. As a consequence,
defects near the drain contribute differently to the recovery trace or an RTN signal than defects near the source and the exponential tail shown in Figure 2.9 decreases.
In the case of an RTN signal, the change of due to an increased readout drain
voltage shifts
of defects in the vicinity of the
drain outside the measurement window. Therefore, such defects can no longer capture and emit charge carriers. Consequently, the number of active RTN defects changes, which affects the exponential
step height distribution. In the case of defects which capture a charge carrier under stress conditions and emit it under recovery conditions, only
can be affected by a changed
readout drain voltage. In particular,
of drain-side defects and defects
located in the center of the channel is shifted towards smaller emission times if
−0.1 V. Thus, such defects still
contribute to the recovery of the device.
However, for defects which capture a charge carrier during stress and emit it during recovery another consequence of an increased has to be considered. According to simulations
considering different random dopant configurations it has been shown that the step heights of the active defects change with
[104]. This effect is
shown in Figure 2.38 for
different random dopant configurations and four different lateral defect coordinates
using 2.2 nm thick
oxide film pMOSFETs with
150 nm and
100 nm. The average behavior of the step height with respect to the
drain voltage at a constant gate voltage
clearly shows that the shape of the curves is affected
by the lateral defect position. For example, while
of defects in the vicinity of the source at
(0 is at source and 1 is at drain) increases for increasing
,
of defects in the vicinity of the drain at
decreases for increasing
. Therefore, the
characteristic can be used as a defect fingerprint and
its lateral position can be extracted.
Figure 2.38: Step height with respect to the drain voltage at different lateral positions: The characteristics for 2.2 nm thick
oxide film pMOSFETs with
150 nm and
100 nm with
different random dopant configurations and four different lateral defect coordinates
simulated using TCAD. The red lines in-
dicate the characteristics with average (solid) and plus/minus standard deviation cubic parameterization coefficients (dashed). Since the shape of the curves is more strongly affected by the lateral trap position than by the random
dopant distribution, it can be used as a defect fingerprint and allows to evaluate the lateral defect coordinate. Figure source: [104].
For the position extraction a simplified technique can be applied [104]. The step heights with respect to
the readout drain bias can be fitted linearly using such a simplified technique. The relative lateral position can be extracted using
with
lateral position in the channel | |
channel length | |
slope of the linear fit | |
constant, found to be approximately |
|
largest step height observed in the measurements, corresponds | |
to |
|
intercept of the linear fit |
This technique is based on the realization that the main information regarding the lateral trap coordinate is given by the slope () and the intercept (
) of the linear fit. The sign of
determines whether the trap is at the
source- or at the drain-side.
is responsible for the proximity of the
defect to one of the electrodes. The shape of
with respect to the lateral defect
position is symmetric (also shown in [17]) and can be approximated by a Gaussian function
with and
.
The standard deviation has been found to be proportional to the channel length. In other words, in experimental data defects which cause small steps in the traces compared to the steps
caused by other defects in the same device, are located in the vicinity of the source or the drain. Defects which cause comparably large
steps are located near the
center of the channel. Depending on the behavior of
(increasing or decreasing with increasing
) the defect’s position can be assigned to either the
source-side or the drain-side. This technique has been applied successfully to measurement data presented in Chapter 5 in order to extract the lateral defect position [104, 105].
The study of degradation mechanisms prevalent in transistors includes a thorough experimental characterization of time-dependent variation and time dependent drifts of MOSFET parameters.
Therefore, different measurement methods and sequences have been developed. In this chapter, an overview is given and the purposes, advantages and challenges of commonly used techniques are introduced. Then, challenges which
had to be faced during the measurements for this thesis, are discussed. In this context, the fact that most of the measurement techniques have been developed for the characterization of either NBTI or
HCD degradation plays an important role. For the discussion of such challenges, the focus lies on the extraction methods applied using
MSM techniques as this method is most relevant for the understanding of the results presented in Chapter 5.
Figure 3.1: Range of stress conditions: Schematic illustration of the different stress conditions NBTI, HCD and
mixed NBTI/HC. The area of stress conditions defines the boundaries of the 2-dimensional parameter space applied in this thesis. Different colors separate the
voltage combinations which trigger different degradation mechanisms, while the color intensity indicates the increasing impact of the stress on the parameter shifts.
As an introduction to this chapter, Figure 3.1 illustrates the stress conditions for triggering both degradation mechanisms, NBTI and HCD, including the so-called mixed NBTI/HC stress conditions applied for the characterization of the unavoidable interplay of both. The
region of stress conditions in this figure shows the 2-dimensional parameter space applied in this thesis. The measurements discussed
in the current and the following chapters were conducted on 2.2 nm
pMOSFETs of a 130 nm commercial
technology (
−1.5 V and
465 mV). One has to distinguish between large-area devices and
nano-scale devices. The first have the dimensions
10 µm and
120 nm or
130 nm, and the second
160 nm and
120 nm or
130 nm.
Using the OTF measurement method, MOSFET parameter shifts are probed directly during operation without interruption of the applied voltages. It was
introduced in 2004 for the purpose of measuring the device degradation during stress conditions
[106], which typically refer to much higher biases than used at nominal operating conditions. This technique aims for the direct characterization of the
evolution.
The basic measurement procedure is shown in Figure 3.2 for BTI measurements. It consists of a periodic modulation of with the modulation amplitude (
) at a certain
drain measurement voltage (
) while
is determined at three measurement
points for each modulation period
. The modulation of
induces a
, which changes over the
modulation periods due to the degradation-induced
during stress. From the
modulation amplitude and the corresponding
the transconductance can be
obtained according to
with
gate stress voltage | |
drain voltage applied during measurement | |
drain current | |
stress time | |
threshold voltage. |
A step-by-step integration of /
gives the threshold voltage shift during
stress:
with
sequential number of measurement | |
number of |
One challenge arises due to the fact that a parameter which is typically measured at a level near the threshold regime, namely , is extracted from a measurement at
stress level where the applied voltages are considerably higher than the threshold voltage. A proper separation of the impact of mobility fluctuations at stress level and
drifts at a level near the threshold
regime on the measurement is, therefore, an issue [107]. The reason is that shifts of the transfer characteristics along the
-axis (
drifts) and “tilts" of the transfer
characteristics (see Figure 3.3) are indistinguishable at the stress level. Such “tilts" are caused by defects located near or at the oxide/substrate interface which contribute to surface
scattering and lower the carrier mobility. Based on a simple SPICE level 1 model, the following three parameter equation meets this challenge and separates the mobility and the
effect from each other:
with
drain-source conductance | |
global mobility (parameter) | |
gate voltage | |
threshold voltage (parameter) | |
leads to an asymptotic approach to a maximum value |
|
the mobility decrease due to surface roughness for high gate fields (parameter). |
The SPICE model has an empirical background and describes above
in the linear
regime rather well, as shown in
Figure 3.3. However, it does not explain the threshold voltage shifts near the regime typically defined as the threshold regime in other measurement methods.
The extraction of depends on the modulation
around
. Therefore, two
measurement points on the transfer characteristics, namely
(
-
/2) and
(
+
/2) or
and
,
respectively, are inserted into Equation 3.3. Assuming that
is known from an initial characterization of the device the two-equation system
containing only two unknowns,
and
, can be solved and as a result the
threshold voltage can be calculated using
with
corresponds to |
|
gate stress voltage | |
amplitude of gate stress voltage modulation | |
drain-source conductance at |
|
asymptotic approach to a maximum value |
|
the mobility decrease due to surface roughness for high gate fields. |
Unfortunately, the extraction of from a measurement at stress level
and not from a measurement in the threshold regime introduces errors. In general, due to the modulation of the gate bias, the stress level changes, leading to a different degradation state than the state obtained after constant stress
over the whole
. For example, it has been shown that
is underestimated with the
OTF method [43]. This systematic error could be minimized by a small modulation amplitude
. However, the
error in
in Equation 3.1 is inversely proportional to
and thus the
smaller the amplitude is, the more error is introduced to
. Since the error in
determines the error of the
extraction in Equation 3.4, the choice of the modulation amplitude affects the statistical error in
[107].
Moreover, the modulation time plays a major role in the obtained degradation state. In order to minimize the change of the degradation state due to the modulation, the time within which the modulation is performed must be as
short as possible. As a consequence, the integration time of the measurement has to be as short as possible. However, a decrease of the integration time in measurements leads to an increase of the statistical error of the measured
. Integration times in the order of
µs or ms lead to a relative accuracy in the measured
of
or less. This corresponds to a statistical error of
of
12 mV, which is too high. In order to
achieve a statistical error of, e.g.,
1 mV in
,
has to be measured with a relative
accuracy of
. With standard equipment, the
integration time required to achieve such a relative accuracy would be more than 20 ms which enlarges the measurement time enormously. Unfortunately, 20 ms is way too long if the prevention of recovery during
the measurement is required. [107]
The OTF method is quite sensitive to mobility changes induced by stress [108] while it is quite insensitive to changes because the
-
curve flattens out at the stress level
[107]. Since
is the parameter of interest, an
insensitivity to the changes of the threshold voltage shift is a considerable disadvantage. Together with the introduced systematic error due to the voltage modulation, this disadvantage makes the OTF
method unfavorable for this thesis.
The CP effect was reported in 1969 for the first time [109]. One milestone in the development of this technique was the investigation and explanation of the method in 1984 [110]. The CP technique is a reliable and precise method for the measurement of defects at the substrate/oxide interface of a MOSFET. Thus, it is often used for the characterization of
HCD, which is typically associated with an increase of such defects. The corresponding experimental setup is illustrated in Figure 3.4 and the
schematic measurement procedure in Figure 3.5. The gate is pulsed by a generator between accumulation, in case of an nMOSFET defined by the low level of the gate voltage () smaller than the flatband voltage (
), and inversion, defined by the high level of the gate voltage (
) higher than
. The source to substrate and drain
to substrate diodes are slightly reverse biased. Simultaneously, the bulk current (
), which consists of leakage currents of
the reverse biased diodes and the
, is measured.
Figure 3.5: Schematic illustration of the charge pumping effect: is measured as a change of
when sweeping
between inversion and accumulation back
and forth.
corresponds to the recombination cur-
rent of trapped minority carriers and majority carriers and is a measure for the interface charge density.
The occurrence of can be explained by the recombination
of majority carriers with minority carriers. A schematic illustration of the gate pulse and the corresponding
is shown in Figure 3.5. When the pulse level is in the inversion phase (pulse level at
), a thin layer in the substrate near the
interface (channel) is depleted of the majority carriers and populated by minority carriers. This leads to a trapping of some of them by existing interface defects. As soon as the pulse drives the MOSFET into accumulation (pulse level at
), the minority carriers leave the
channel and the majority carriers flood it. Simultaneously, some of the interface defects with energies close to the valence band or conduction band can emit their trapped charges by thermal emission before the accumulation phase is
reached due to the finite rising and falling slopes. These minority carriers are pushed into the substrate while switching to the accumulation phase without any contribution to
because the overall amount of positive
and negative charges is not changed throughout this process. By contrast, all other trapped minority carriers recombine with the majority carriers in accumulation, which gives rise to a net flow of charge into the substrate. This can
be measured as
and is directly proportional to the
pulse frequency and the mean interface-state density. In the accumulation phase, some of the majority carriers are trapped by interface defects. Driving the MOSFET back into inversion results in a
similar process as described for the transition from inversion to accumulation but with opposite carrier types.
As a consequence of the thermal emission of carriers during the rising and falling edge of the pulse, only interface defects within a particular energy range around midgap, which is smaller than the entire silicon bandgap, can be
measured in . The energy boundaries in the lower
and upper half of the bandgap, defining the active energy interval, are given by [111]
with
boundary in the lower / upper half of the bandgap | |
intrinsic Fermi level | |
pulse rise / fall time | |
pulse amplitude | |
thermal drift velocity | |
capture cross section for holes / electrons | |
intrinsic carrier concentration. |
Figure 3.6: Effective channel length: Due to lateral doping profile the local and
differs along the channel. Depending on
and
different channel areas contribute to
. For pulse (a) only for the lightly doped
regions near the source and the drain contribute to
. Therefore the effective length is
. For pulse (b) a broader region, in-
cluding the central region of the channel, contributes to
. Therefore the effective length is
. Figure source: [112].
For the calculation of , it has to be considered that dependent
on the chosen
and
only a particular fraction of the
channel is probed during a gate pulse as shown in Figure 3.6 with two pulses (a) and (b) [112]. Due to the lateral doping profile along the channel (regions near
source and drain are typically lightly doped) the local
and
differ along the channel. The
requirement for driving one particular lateral position from accumulation to inversion is met if
and
at this position. Pulse (a) meets this
requirement only for the lightly doped regions near the source and the drain but not for the central region because
. Summing up the length of the
regions, which contribute to
for pulse (a) results in the effective
length
. By contrast, pulse (b) meets the
requirement for a broader lateral range, including the central region of the channel, resulting in an effective length
. In this regard, the effective area,
which corresponds to the fraction of the channel probed during the gate pulse, can be calculated according to
with
active channel area | |
effective channel length | |
gate width. |
Figure 3.7: Constant amplitude CP method: is swept through a broad voltage range
from
to
while rise time
(
), fall time (
) and pulse am-
plitude (
) are constant as shown on the left
hand side.
(
) shown on the right hand side increases
with increasing
as long as
, is at its maximum when both
and
are fulfilled, and finally decreases with
further increase of
when only
is satisfied. Figure source: [112].
Finally, the charge pumping current can be written as [110, 112]
with
pulse frequency | |
electron charge | |
gate width | |
boundary in the lower / upper half of the bandgap | |
interface-state density. |
The measurable depends on the active energy interval,
which is affected by experimental parameters like
and
of the pulse, the
as well as
. This allows for an energetic profiling by modification of the experimental parameters.
Moreover, due to the fact that
and
depend on the lateral position in the
MOSFET, the spatial distribution of interface defects can also be analyzed. As a result, different CP techniques have been proposed [112].
For example, the constant amplitude CP technique uses a variable and constant
,
and
as shown in Figure 3.7.
is swept through a broad voltage range
from
to
. This leads to an
(
) which shows first an increasing
behavior with increasing
as long as
. Then the charge pumping current
reaches its maximum when both
and
are fulfilled. Finally
decreases with further increase of
when only
is satisfied. In this technique, the
active energy interval remains constant but in fact, different channel areas contribute to
, depending on
and
as shown in Figure 3.6 schematically. Although it seems quite advantageous to distinguish between contributions of central interface defects and defects in the lightly doped regions based on the
(
) shape, such a characterization
technique remains qualitative because the particular effective channel area (
) contributing to
at each
is unknown.
By contrast, remains at a fixed value for the whole
measurement satisfying
while
is swept through a broad voltage
range. As a consequence,
is a function of
only, which leads to a probing of the
channel from outside to inside in a symmetrical way if
is swept from
to
. In order to distinguish between
local and energetic information, the active energy interval defined by the energy boundaries given in the Equations 3.5 and 3.6 has to be
fixed. This is realized by adapting
and
after every
step as a compensation of the
increasing
. Pure energetic profiling is
enabled if
and
are fixed at
and
, respectively, and either
or
are changed. Furthermore, by variation
of
the active energy interval can be broadened or narrowed.
Both, energetic and position profiling of defects at the interface, typically realized with standard equipment, has made the CP method a widely used characterization technique. It gives a deep insight into degradation mechanisms associated with an increase of interface defects, typically HCD.
Figure 3.10: C-V curves for a pMOSFET: The shape of the C-V curves in
Figure 3.10 changes during stress and recovery. From these changes the information about the defects at different energy levels contributing to degradation and recovery as
well as about and
can be extracted.
In addition to the CP method, the C-V method allows for an energetic profiling of defects as well. The C-V technique was introduced
in 1960 in order to determine the majority carrier concentration in semiconductors [113]. Meanwhile, this method is also used for tracking the and
shifts in MOSFETs due to previously applied stress [114, 115]. As shown schematically in Figure 3.8, the basic experimental setup can be realized by the application
of a bulk voltage (
) at the drain, bulk and source contacts
and a simultaneous measurement of the
. The applied
signal is a superposition of a DC offset,
which drives the MOSFET from accumulation to inversion, and a small AC component with an amplitude typically around 50 mV. Due to the gate capacitance (
), the simultaneously measured
is phase-shifted as illustrated in
Figure 3.9. Using an equivalent circuit diagram
can be calculated from the
and
signals.
Typical curves of with respect to the DC offset of
are shown in Figure 3.10. When sweeping the DC component from accumulation to inversion, a depletion layer near the substrate/oxide interface forms because the majority carriers are forced away into
the substrate. The remaining fixed ionized acceptors or donors build up a depletion charge and reduce the total gate capacitance. As soon as the minority carriers at the interface exceed the majority carriers and an inversion layer is
created, the gate capacitance increases again. From the change of the C-V shape in Figure 3.10 during stress and recovery phases, the
different energy levels contributing to degradation and recovery as well as
and
can be extracted. This allows for a
thorough characterization of degradation mechanisms like BTI and HCD.
Figure 3.11: MSM sequence: The applied gate and drain voltages (S) are interrupted periodically in order to characterize the degradation state of
the device, e.g., by taking an -
curve (M). The monitored parameter, e.g.,
is extracted and the degradation over
time is obtained. The overall stress time is obtained as
.
One widely used method for the experimental characterization of device degradation is the MSM technique. This method comprises basically of the following phases (also shown in Figure 3.11):
1. Measure: The virgin device is characterized.
2. Stress: The device is subjected to a stress bias, which is typically much higher than the nominal operating conditions.
3. Measure: The stressed device is characterized.
4. The cycle comprising of the second and third phase can be repeated with either constant or increasing .
The second phase does not necessarily have to be a stress phase, it could also be a recovery phase. The main difference between stress and recovery is the applied voltages. While stress is associated with biases typically much
higher than the nominal operating conditions, recovery is associated with either no bias applied or biases around . The characterization of the stressed
device in the first and third phase can be realized by either taking an
-
curve (e.g., in order to obtain
or
) or by applying one of the
previously mentioned measurement methods, the CP method (e.g., in order to obtain the HCD induced interface state creation) or the C-V method. Consequently, the experimental setup has to be chosen according to the measurement method.
Especially for measurements, it has been
found that MSM is quite disadvantageous. As discussed in Section 2.1, degradation comprises of a permanent and a recoverable component.
Because of the recoverable component,
recovers as soon as the stress
is removed or as soon as the bias is switched to a lower voltage. Therefore, the overall device degradation state will be different when obtained by interruptions of stress than if the stress bias is applied continuously. Moreover, the
MSM method cannot capture short-term effects of
degradation and recovery
(discussed in Subsection 2.1.1). The interruptions of the applied voltages, although as short as possible, can take 50 ms or more. Therefore, the degradation or
recovery state of the device is distorted because the interruption of the applied voltages might reverse the impact especially of short-term effects on device characteristics. Therefore, the MSM method
often cannot capture this impact, which makes reliable short-term measurements (
1 s or
1 s) impossible.
In order to overcome these disadvantages, two innovative and fast measurement methods have been introduced, which can obtain without any interruptions of
stress or recovery. These two methods are summarized in the following section as eMSM methods.
The eMSM method consists of single point measurements of either (corresponds to the constant voltage (cv) method in this thesis) or
(corresponds to the constant current (cc) method in this thesis) at a point near
during the recovery phase and a
subsequent
extraction. The basic
measure-stress-measure sequence of this method is quite similar to the sequences discussed in the previous section. The main differences are that the measure phase refers to a recovery phase where
or
is measured and that neither stress nor
recovery is interrupted. Both measurement methods are discussed and compared in the following.
The cv method and and the cc method have been introduced in the literature as the fast- method and the fast-
method, respectively [31, 39, 40,
116]. The extraction of
for both methods is shown in
Figure 3.12.
• The cv method: is measured by recording
at a constant voltage, typically near
and subsequently converting
to
using the initial
-
[31, 116].
• The cc method: is monitored by recording
, which is controlled by a feedback loop
of an operational amplifier to achieve a constant drain current, typically near the threshold current [39].
Figure 3.12: Two different methods to extract the threshold voltage shift during recovery: The cv and cc meth-
ods. Top: Characteristics of an unstressed device (blue) and of a device after degradation (red). During the measure phase the parameters and thus the shape of the -
characteristics drift towards their initial
values. Bottom:
is monitored using either the
cv method (orange) by recording
at a constant voltage
near
and mapping to
using the initial
-
or the cc
method (green) by recording
at a constant current
near the threshold current.
The eMSM technique allows for a more extensive analysis of compared to other
techniques. First, eMSM allows for short-term measurements (
1 s after the recovery phase is
triggered) because the recovery is measured without any distortions of the degradation or recovery state which is in contrast to the MSM method (discussed in the previous section and in
Subsection 2.1.2). Furthermore, due to the fact that no bias modulation is applied during the stress phase which is the case if the OTF technique is
used, no systematic error is introduced by periodic changes of the gate bias. Moreover, considering a statistical error of
1 mV in
, the relative accuracy in the
measured
needs to be
in the eMSM technique, which is achievable
with reasonable integration times. Furthermore, this technique is insensitive to mobility changes induced by stress in contrast to the OTF technique [108]. Finally, the information about the recovery
evolution of the MOSFET in eMSM measurements allows for the observation of both, the recoverable and the permanent component of the
degradation [71]. In the
context of
measurements, these facts
make the eMSM technique advantegeous.
Both extraction methods, the cv and the cc method, have been developed mainly for BTI measurements and provided equivalent
results for NBTI stress. However, recent recovery measurements recorded after mixed NBTI/HC stress have shown that extracted from the cv method and from the cc method can differ significantly. These deviations might lead to inconsistent model parameters and lifetime predictions. Therefore, in this section, the
difference between both measurement methods is thoroughly analyzed and discussed considering the shifts of MOSFET parameters like
,
,
and
.
The basic experimental setup which has been introduced for TDDS measurements in 2010 [16, 33, 40] is shown in Figure 3.13. The voltages
applied to the gate and drain contacts are provided by constant voltage sources while is measured simultaneously by a
transimpedance amplifier. The feedback resistor of the transimpedance amplifier
defines the measurement range for
. The evolution of
,
and
over time for all three phases is shown
in the measurement procedure in Figure 3.14.
Figure 3.14: Measurement procedure for the cv method: After the initial characterization of the unstressed device, and
are applied. During
degrades. Afterwards, the measurement
voltages gate voltage at recovery conditions using the cv method (
) and
are applied and
recovers. During the last phase,
is recorded in order to ex-
tract
.
The extraction for the cv method is illustrated in the left bottom panel of Figure 3.12. During the first measure phase an initial
-
characteristics within a narrow gate bias
window around the
is measured at
(typically
−0.1 V in the measurements performed for this thesis) in order to characterize the unstressed device. The corresponding drain current is labeled with
in the left bottom panel of Figure 3.12:
Thereafter, the device is subjected to a stress bias ( and
) for the time
and immediately afterwards to
recovery bias (
and
) for the time
. As a result of the degradation of
during stress, directly after stress release
the
-
characteristics are shifted and the drain
current is reduced to
:
While subjecting the device to recovery conditions, recovers from its reduced value towards
its initial value and is monitored simultaneously. In a postprocessing step, each measured value of
is transformed to a
voltage
, which corresponds to the
gate voltage at
on the initial
-
characteristics (
,
, ...). Finally, the threshold voltage shift can be calculated as
Obtaining from the cc method requires a measurement setup as shown in Figure 3.15 [39]. Similar to the cv method, the gate and drain
voltages during the stress phase as well as the drain voltage during the recovery phase are provided by constant voltage sources. In contrast to the cv method, in the cc
method the drain current during the recovery phase is controlled by a feedback loop of an operational amplifier in order to achieve a constant value, typically near the threshold current. The evolution of
,
and
over time for this case is shown in the
measurement procedure in Figure 3.16.
Figure 3.16: Measurement procedure for the cc method: After the initial characterization of the unstressed device, and
are applied. During
degrades. Afterwards, the measurement
voltage
is applied while
is held at the constant value drain
current at recovery conditions using the cc method (
). During the last phase,
recovers and is recorded in
order to extract
.
obtained using the cc method does not require a transformation since
can be calculated directly as
shown in the right bottom panel of Figure 3.12. First, the gate voltage labeled with
which corresponds to the measurement current
is obtained by recording
for a short duration at
recovery conditions (drain current is held at
at
):
Then, the device is subjected to a stress bias ( and
) for the time
and subsequently to the recovery bias
while the drain
current is held at
for the time
. The consequence of the
-
characteristics shift due to the device
degradation during stress is a reduced gate voltage
directly after stress release:
During recovery, the gate voltage recovers towards its initial value and is monitored simultaneously. Finally, the threshold voltage shift can be calculated for all :
Figure 3.17: Difference between considered device variability and not considered device variability: Top: Variability is considered as the recovery conditions are chosen
in equidistant intervalls to for each device individually. This
ensures that the measurement current for the cc method corresponds always to the measurement voltage in the cv method indicated by the black markers. Bottom:
Variability is not considered as the recovery conditions are fixed for every device so that in average
.
For devices which deviate from the average characteristics the recovery conditions set in the cv method (indicated by the orange markers) differ from recovery conditions set in the cc
method (indicated by the green markers), which leads to a significant difference of the extracted
.
The cv method and the cc method can be considered equivalent only if the following requirements are met. The -
characteristics shifts along the
-axis during stress and recovery and the
shape (slope and curvature) of the curve section between
and
in the left bottom panel of Figure 3.12 equals the shape of the
curve section between
and
in the right bottom panel. In other words, neither
nor
change significantly during the experiment and the device-to-device variability is
considered properly by setting each measurement point according to
0 s
. In fact, all MOSFET parameters drift during stress and recovery differently, strongly depending on the stress conditions. As a result, the shapes of the unstressed and stressed
-
curves differ from each other, which
leads to
as it will be discussed in the next subsection.
For a comparison of the different threshold voltage extraction methods 21 large-area devices were measured. The measurements were performed at
130 °C (controlled by a thermo chuck) using fabricated silicon
wafers. Initially,
-
characteristics for the linear (
−0.1 V) and saturation (
) regime were taken. Considering the
-
in the linear regime,
was extracted as the gate bias
where the extrapolation of the
-
slope at its maximum transconductance
intercepts the x-axis (extrapolation in the linear region method in [2]). This results in
mV. During the subsequent
stress/recovery measurements, each of the 21 devices was subjected to one combination of gate and drain stress voltage (
is −1.5 V,
−2 V and −2.5 V,
is 0 V,
−0.5 V, −1 V, −1.5 V, −2 V, −2.5 V and −2.8 V) for a stress time
1.1 ks and subsequently
is measured for a recovery
time
3 ks. Immediately afterwards,
-
characteristics for the linear region and
in the saturation regime are measured in order to compare the characteristics of the tested and the virgin devices. Doing so, the maximum transconductance shift (
),
, the saturation drain current shift (
) and the sub-threshold swing shift (
) are extracted for each device. Furthermore,
and
was extracted
from the
-
characteristics of the degraded devices
and the unstressed devices in two different regions near
of the initial curve: the
subthreshold region, abbreviated with sub in the following, and a region above the threshold voltage. Two cases are distinguished, both illustrated in Figure 3.17: with and
without device variability.
In the first case, the recovery conditions are chosen in equidistant intervals to for each device (top panel in
Figure 3.17). This means that
or
has to be set individually,
depending on
. In the shown measurements,
recovery conditions were defined as
mV or
mV
for the subthreshold region and
mV or
mV
for the region above
, both at
. This ensures that the
measurement current in the cc method corresponds always to the measurement voltage in the cv method. In the second case, the recovery conditions are set to fixed
values, independent from
, which is
−0.43 V or
−13 µA in the subthreshold region and
−0.6 V or
−60 µA in the region above
in the measurements performed
for this thesis. On average, the requirement
is met but this does not hold true for every particular device as shown in Figure 3.17 bottom. If it holds true, strongly depends on the
deviation of the individual
-
characteristics from the average.
At a first glance, it seems that the second case is easier to implement. The reason is that it requires only one analysis per device architecture and device dimensions prior to all experiments in order to determine an average -
characteristics and define the recovery
conditions. By contrast, the first case needs an
-
analysis per device prior to each
experiment, which means much more effort for the experimentalist. However, the second case means that the recovery conditions differ for the cv and the cc method
depending on the deviation of the individual
-
characteristics from the average. From
Figure 3.18 it can be seen that different recovery conditions lead to different
recovery traces. This
introduces a difference between
and
. The following
results lead to a similar conclusion.
Figure 3.20: Correlation of with the degradation of MOSFET parameters: Each point in the scatter plots
corresponds to the degradation after subjecting the MOSFET to a particular
-
combination. The relative difference
increases with larger degradation and it is in average lower for the subthreshold
region.
In Figure 3.20 the relative difference between extracted from the cv method
and extrated from the cc method (
) is calculated as
and is plotted against the relative degradation of ,
,
, and
under consideration of the device variability. Each point in the scatter plot
corresponds to the measurement of one particular device, which has been subjected to one particular
combination. Additionally, in order to analyze if the
difference between both measurement methods correlates with the degradation of MOSFET parameters, the Pearson correlation coefficient as a measure for a linear correlation between
and
,
,
, and
is given for each region:
for the subthreshold region and
for the region above
. As can be seen,
correlates differently with the relative change of the MOSFET parameters:
• increases with larger degradation of
,
,
and
,
• on average, is lower for the subthreshold region,
• the maximum difference 6 %,
• correlates strongly with
in the subthreshold region but weaker in the region above
and
• correlates strongly with
,
,
in the region above
but weaker in the subthreshold
region.
The correlation between and
,
,
, and
is dominated by the impact
of the MOSFET parameter shift on the change of the slope and the curvature of the
-
characteristics. While
characterizes essentially the slope and the curvature in the subthreshold region,
,
, and
affect the slope and
curvature at
mV. Thus, a change of
during stress and recovery affects mainly
in the subthreshold region. However, the analysis shows that
does not exceed 4 % if the measurement point is chosen in the
subthreshold region.
If the variability of the MOSFETs is not considered and the measurement points are chosen at fixed values near the mean value of , the main observations change.
Subfigure 3.19b shows the correlation between
and
,
,
, and
. Some observations are
comparable to the observations in Subfigure 3.19a:
increases with larger degradation and
is lower for the subthreshold region on average. However, the maximum
difference
10 %, which
interestingly occurs at low degradation, is higher, and the correlation with all parameters is weaker than if variability is considered. Due to the fact that
0 s
does not necessarily equal
the two sections measured
with the cc method and the cv method can differ in slope and curvature even if the degradation is low.
Recorded recovery during the measure
phase confirms these results. For low degradation of the parameters (
,
,
, and
are less than 2 %),
the cc method and the cv method show quite comparable results. By stark contrast, degradation caused by mixtures of BTI and HCD or pure HCD, where the
parameter degradation exceeds 4 %, leads to completely different
traces. Figure 3.21 shows two recovery traces where it can be seen that
−10 % at low
but increases with
, which indicates that the evolution of
the slope and the curvature during the measure phase can differ significantly. For example, if
does not recover but
does recover, the shape of
the
-
characteristics distorts during the
measure phase. This is a realistic example since the transconductance is affected by scattering of channel carriers at charged interface states. The number of such interface states increases during stress and as a consequence, the
transconductance reduces. As discussed in Chapter 2, interface state barely recover [22, 24, 93, 97, 117].
Figure 3.22: Unstable stress voltages in the cc method: The applied voltages are not stable during stress as soon as
0 V. As soon as the device de-
grades its
reduces and the ratio between the drain-
to-source voltage and the voltage over the serial resistance
changes. Both, the voltage between
the drain and the source contact (
) and the voltage between the gate and
the source contact (
) drift slightly, which results in voltage
differences
and
compared to the unstressed de-
vice.
From this analysis, it cannot be concluded which of both techniques should be chosen for measurements. Nevertheless,
the advantages and disadvantages of both measurement methods are discussed briefly. The constant voltage setup as used in [16, 40] measures the drain current with a transimpedance amplifier where the feedback resistor defines the
measurement range for
during stress as well as during the
measure phase. Due to the fact that
can vary between the stress and
measure phase by a few orders of magnitude and in order to ensure a proper measurement resolution during the measurement, the feedback resistor has to be changed between stress and recovery. Thus, an additional delay on the
order of ms is introduced and important information regarding the evolution of
during the first ms after
stress is lost. By contrast, the cc setup as proposed in [39] minimizes the delay between the stress and measure phase because no feedback resistor has to be changed between both phases. As a
consequence, the cc method is advantageous in the case that the degradation of the device cannot be estimated prior to the MSM measurement, which is a requirement
for the proper choice of the feedback resistor in the constant voltage setup. However, the requirement that the stress voltage applied to the gate contact has to be constant in order to avoid changes of the degradation state of the
device makes the cv method easier to implement (as also discussed in [107]), e.g., using standard equipment. The reason is that the MSM cycles can be realized with one
voltage source. This is not the case for the cc method where a voltage source is required during stress and a current source is required during recovery.
Further measurements using both methods showed that can be even higher, up to 100 %. One error has not been taken into
account so far. By taking a look at the measurement setup for the cc method in Figure 3.15 it becomes clear that in the case that
0 V the stress conditions are
not stable as shown in Figure 3.22. As soon as the device degrades, its
reduces and the ratio between the
drain-to-source voltage and the voltage over the serial resistance
changes. The consequence is that
the stress conditions of the device drift slightly during
. It has already been discussed that
changes of the stress conditions over
lead to a different degradation state
compared to the state after stable stress conditions.
As a comparison, Figure 3.23 illustrates that the setup for the cv method (see Figure 3.13)
provides stable stress voltages. However, it has to be mentioned that the constant offset around 30 mV means that the set stress voltages do not correspond to the applied voltages. This offset introduces a systematic error for
further modeling attempts. As shown in Figure 3.24 even slight deviations of the stress conditions, although stable, can make a difference for the recovery traces.
Both, the drift of the stress voltages using the cc method as well as the constant offset in the cv method, lead to a relative difference between and
higher than
obtained in Figure 3.20. Since a constant offset is easier to be considered for modeling attempts, the cv measurement method was applied
for the results presented in the following chapters.
Due to the intensive down-scaling of MOSFETs, the gate area has reached dimensions in the nanometer regime where single capture and emission events of oxide defects are measurable. In this
context, the observation of the so-called RTN became more likely. This phenomenon (shown in Subfigure 2.14b) has been known and modeled since
the 1980s [16, 48, 62] and describes the discrete changes in the conductance of electronic devices generated by capture and emission of charge carriers by individual oxide defects. The capture and emission events can be measured as a
change of with either the setup for the
cv
extraction shown in
Figure 3.13 or the setup for the cc
extraction shown in
Figure 3.15.
RTN analysis includes the characterization of the mean values of the characteristic and
at different bias and
temperature. Therefore, a
trace is recorded using linear
time steps. For a proper analysis, the trace has to contain at least ten capture and emission events to calculate a mean value of the characteristic times
with
mean capture/emission time | |
number of capture or emission events | |
individual capture/emission time of one event. |
Using a step detection algorithm like the Canny algorithm [118] or a Hidden Markov Model, the discrete steps are located in time and as well as
are extracted for each pair of
emission and capture events
. As a result, the mean values
and
provide important information about the behavior of
the defect which has caused the steps in
.
The characterization of defects using the RTN analysis is only feasible for defects with rather similar capture and emission times, where is fulfilled. This limits the range
of bias conditions drastically because of the properties of material defects in experiments as discussed in Subsection 2.1.3. Both,
and
change opposite to
. As a result, RTN analysis can be applied only within a narrow window around the gate bias of the intersection point of
and
. For a full characterization using the NMP model as required for an extraction of the important parameters which describe the nature of the defect, the characteristic capture and emission times have to be measured over a broad
range.
As soon as is not within the narrow window around
the intersection point of
and
, two cases can be distinguished, either
or
. The first corresponds typically
to the defect properties at recovery conditions, where
is near
and the second corresponds typically
to the defect properties at stress conditions, both discussed in Subsection 2.1.3. This means that
,
and
,
can be obtained by a kind of eMSM method, which has been developed particularly for the extraction of defect characteristics in experiments, the TDDS framework.
The TDDS framework has been introduced recently with the main purpose to characterize single oxide defects in MOSFETs [40]. In general, both, the setup for the
cv extraction shown in
Figure 3.13 and the setup for the cc
extraction shown in
Figure 3.15 can be used as experimental setups. However, in the following, the focus is on the cv setup since this method is in the focus of this
thesis. The measurement procedure corresponds basically to a sequencing of the stress and recovery phase of the eMSM technique after the initial characterization of the device (Figure 3.14) including several postprocessing steps:
1. Characterization of the unstressed device by taking an initial -
.
2. Subjecting the device to a stress bias for .
3. Monitoring for
providing its recovery behavior over
many decades in time.
4. Repetition of the second and third phase, for example times.
5. Mapping to
as explained in
Figure 3.12.
6. Postprocessing of the data by extractin step heights and step times.
As already discussed in the introduction, the capture and emission events of defects affect device characteristics like . As long as the energy level of the
defect is located in a certain area in the band gap, it can be shifted above the Fermi level by applying a stress gate bias typically above nominal operating conditions and shifted below the Fermi level by applying a recovery gate bias
typically around the threshold voltage. Depending on the detailed defect configuration the defect can capture and emit a charge carrier at stochastic times. Such charge exchange events between the oxide and the channel can be
measured as stepwise shifts of
. While the step heights
cannot be resolved in large-area devices due to the small impact of one charge exchange event, they can be experimentally assessed in nano-scale devices containing only a handful of defects [17, 18].
Due to the fact that the capture and emission events are stochastic, TDDS requires a number, e.g., , of stress/recovery experiments to capture statistics for a reliable characterization.
The top panel of Figure 2.8 shows typical recovery measurements containing the steps of five defects enumerated with 1, 2, 3, 4 and 12. These defects have each captured a charge carrier
during the previous stress phase and emit this charge carrier during the recovery phase, which causes a step in the
recovery trace. In a
postprocessing step,
and
are extracted for each step and
can be binned into a two-dimensional histogram shown in the bottom panel Figure 2.8 bottom. As a result, a cluster for each defect forms in the spectral map, which is an unambiguous
fingerprint of the defect. By assignment of each cluster to a certain defect, the mean values for
and
can be calculated.
Figure 3.25: Occupancy with respect to the stress time: With increasing stress time the occupancy of the defect D1 increases. As a consequence the number of emission events
increases. The occupancy can be calculated for each stress time as the ratio between the number of emission events () and the number
of recovery traces (
). By fitting the measurement points with
an exponential function (Equation 3.11,
can finally be extracted.
In contrast to ,
is measured indirectly. Two
reasons can be mentioned in this regard. In BTI measurements no
is applied and thus
is nearly zero. Therefore, the charge
exchange events cannot be measured in
. In mixed NBTI/HC stress measurements the charge exchange events cannot be measured, especially for high
. In addition,
considering the number of charge carriers in the channel at stress conditions and the measurement range defined by the feedback resistor of the transimpedance amplifier the single steps cannot be resolved at stress. As a result,
has to be extracted from the
occupancy with respect to
, which is shown in Figure 3.25.
In Figure 3.25 of a defect named D1 is
extracted. This is done by exploiting the stress time dependence of the occupancy. From this, the occupancy can be calculated as the ratio of the number of emission events (
) to the number of recovery traces (
). The occupancy
/
in respect to
follows an exponential function
according to Equation 2.18:
with
occupancy, experimentally characterized as the ratio | |
between |
|
gate stress voltage | |
drain stress voltage | |
stress time | |
corresponds to |
|
capture time. |
By fitting the measurement points with this exponential function, can finally be extracted. The
spectral maps illustrate that with increasing
the intensity of the cluster assigned to
the defect named D1 increases as well.
One challenge of the TDDS, which has to be mentioned at this point is that defects with similar and
cannot be distinguished in the
spectral map because they cause clusters at similar positions. Often, this challenges the full characterization of a defect because the defect characteristics have to be recorded for a wide range of stress and recovery bias conditions.
Each change of the stress bias results in a shift of
,
and/or
. In devices with more than four experimentally feasible defect clusters in the spectral
map it is quite likely that two defects cross their paths in the spectral map and thus cannot be distinguished. This limits the voltage range in which defects can be characterized fully. In most of the measurements, this leads to a
pre-selection of defects.
However, the TDDS is one of the most reliable techniques in the context of single oxide defect characterization which has led to numerous conclusions as already discussed in Chapter 2. Although it has been developed for BTI measurements, it has been experienced that it is also reliable in mixed NBTI/HC measurements, presented in Chapter 5.
Typical capture and emission times of oxide defects vary by many orders of magnitude, from µs to weeks, depending on their properties, the temperature, and the bias conditions applied to the MOSFET. However, especially in TDDS measurements the experimental window is limited due to the fact that each measurement contains, e.g., stress/recovery cycles. In order to capture the characteristics of a defect with a
characteristic emission time of one week, the measurement would take approximately two years for one gate and drain voltage combination. If it is taken into account that a thorough characterization of defects requires more than one
measurement, such measurement durations are not feasible. However, defects with very large emission times are of special interest because they contribute among others to the permanent component of degradation, which is expected
to dominate the device lifetime distribution. Therefore, their thorough characterization would be essential.
Not only defects with large emission times can be a challenge for the experimental characterization. Defects with emission times smaller than are a challenge as well. One
possibility to overcome these challenges is to accelerate or to slow down the charge carrier exchange by changing the temperature during the stress and recovery phases in TDDS measurements
independently. The impact of
on
and
is discussed in
Subsection 2.1.3. In order to shift
and
lying outside experimentally
feasible time slots, defined temperature ramps (one example is shown in Figure 3.28) can be applied during stress and/or recovery. For this purpose, an in situ heating technology
for temperature accelerated measurements has been introduced recently [119–121].
Such temperature accelerated measurements can be based on local heaters realized as polycrystalline silicon wires (poly-heater). They are processed near the MOSFET and electrically isolated as
shown in Figure 3.26. In contrast to the experimental setups for the extraction in eMSM measurements, the poly-heater-device system has two additional contacts for the application of a voltage to the poly-heater (see Figure 3.27). As long
as no voltage
is applied to the wires, the MOSFET and the poly-heater are held at a fixed device temperature (
) and at a fixed poly-heater temperature (
), respectively, both corresponding to
the thermo chuck temperature (
):
. When a voltage is applied to the
wires resulting in a current flow through the poly-heater (
), the dissociated heat corresponding to
the power dissipated in the poly-heater (
) elevates
first. Immediately afterwards, a
temperature gradient forms vertically across the device stack because
. As a consequence,
is elevated as well:
.
Figure 3.27: Experimental setup for temperature accelerated measurements: The voltages applied to the gate and drain contacts are realized as constant voltage sources and is measured using a transimpedance am-
plifier. The heating with the polyheater is realized with a constant voltage source voltage applied to poly-heater (
). Simultaneously the poly-heater cur-
rent
is measured.
In order to assign the correct to
, the system has to be calibrated prior
to the measurements. The calibration procedure is shown schematically in Figure 3.29. The calibration consists of the following steps:
1. is obtained at different
at
0 W over a wide range of temperatures. It has to be considered that
has to be chosen in such a way that no stress is
introduced to the device, e.g., in the subthreshold region near
.
2. is obtained at different
at a fixed
, which corresponds to the temperature minimum (
) of the setup.
3. ) and
are fitted with a polynomial fit of first or second
order.
4. With the coefficients of the fits, is interpolated for arbitrary poly-heater power at a
certain
.
Figure 3.29: Schematic poly-heater calibration: is obtained at the required
for
0 W and at different
at a fixed
, which corresponds to the
of the setup.
and
are fitted with a polynomial fit of first or second order.
With the coefficients of the fits,
is interpolated for arbritrary poly-heater power at a
certain
.
This calibration method can also be applied to obtain the temperature of the poly-heater . In this context, the increase of the poly-heater resistance (
) with
caused by the reduction of the carrier mobility of the polycrystalline silicon wires can
be characterized. Therefore,
at
0 W and
at
are measured and fitted with a
polynomial fit of first or second order. With the fitted coefficients
can be interpolated. For such calibrations it has to
be considered that the coefficients of the polynomial fits are valid only for a certain
. If the poly-heater is used at a
different
the calibration has to be repeated
for each required
.
The poly-heater technique is able to reach temperatures far beyond the scope of conventional thermo chuck systems. While the latter are typically used up to 200 °C, poly-heater systems can elevate up to 300 °C and more.
As a result, the probing temperature range of the poly-heater technique is much wider than the one used for its calibration. In order to make use of this wide range, an analytical expression for
has been proposed [121]. Unfortunately,
does not depend linearly on
but exponentially. A linear dependence
is associated with simple Joule heating where the thermal resistivity (
) of surrounding materials does not play a role. By contrast, in the case
of the poly-heater system
increases simultaneously with the temperature increase. Thus the
functional dependence of the device temperature on the power supplied to the heater is an exponential function:
with
device temperatre | |
poly-heater power | |
chuck temperature | |
thermal resistance of the substrate | |
constant | |
constant. |
Figure 3.30: Heating and cooling characteristics: For
−60 °C. (1) Left: The heater power is abruptly turned
on. Right: Within 1 ms the maximum of
is reached. Afterwards,
tends to decrease slightly for approxi-
mately 1 s until the thermal equilibrium between heater, wafer and chuck is restored. Due to the delayed thermal coupling of poly-heater and MOSFET,
needs up to 10 s until stabi-
lization. (2) Left: The heater power is abruptly turned off. Right:
decreases to zero within 1 ms
and
needs up to 10 s until it reaches
. Figure source: [120].
As shown in Figure 3.30, this type of temperature elevation is quite fast compared to other heating setups, e.g., the furnace which was used for the temperature control of
devices mounted on a ceramic package in this thesis. As soon as a certain voltage is applied to the poly-heater, it takes approximately 1 ms until the maximum is reached, a process mainly limited by
the finite speed of the voltage source [121]. Afterwards,
tends to decrease slightly for
approximately 1 s because
increases due to the elevated
until the thermal equilibrium between
heater, wafer and chuck is restored. Due to the delayed thermal coupling of poly-heater and MOSFET,
increases after turning on the
poly-heater and needs up to 10 s for the stabilization. Then,
remains constant until the heater is
turned off again. After turning off the heater power,
decreases to zero within 1 ms,
again mainly limited by the finite speed of the voltage source, and
needs up to 10 s until it
reaches
finally. As a comparison, the
furnace which was used for the experimental characterizations of MOSFETs mounted on ceramic packages in this thesis needs more than 30 min until the thermal equilibrium of the system is
restored after a temperature change. Due to the significant temperature switching speed, the poly-heater system is quite promising for the realization of fast temperature ramps [119].
However, the possibility of an application of defined temperature ramps is not the only advantage of a poly-heater system. It can also overcome limitations typically associated with a thermo chuck. One limitation is that switching
of the temperature in conventional setups, where is controlled by the thermo chuck and
the MOSFET is contacted by probe-needles, the probe-needle contact can get lost. The reason for this is that heating and cooling a wafer on a thermo chuck results in a considerable thermal expansion
of the probe-needles. As a consequence, a continuous manual needle adjustment is required when
is changed. By contrast, heating with
the poly-heater is local and causes no thermal expansion of needles and pads. This enables a change of temperature simultaneously with the measurement cycles without introducing additional delays due to manual needle
adjustments.
A hardware and software application for temperature control of local poly-silicon heater structures based on the setup in Figure 3.27 has been developed within the TDDS framework [122]. This allows for controlled temperature pulses or ramps during device recovery within the TDDS sequence of stress and recovery cycles. The poly-heater setup can be easily realized with standard equipment as well. Unfortunately, during the measurements with this application, difficulties arose, which are discussed in the following.
Figure 3.31: Dependence of the drain current on the dissipated poly-heater power in packaged large-area devices: The left panels show and
after the poly-heater is turned on and
the right panels show
and
after the poly-heater is turned off. While
the stabilitzation of
needs approximately 10 ms, the
stabilization of
needs 30 min at least (100 s
are shown in this figure).
For the experimental characterization only poly-heater MOSFETs mounted on a ceramic package were available, which introduces a number of complications due to two facts. On the one hand, a
ceramic package has no defined heat sink as the thermo chuck in the previously described setup. On the other hand the thermal resistance of the materials surrounding the heater/device system is higher in a package than in the
poly-heater-device-chuck-system shown in Figure 3.26 and described in [112, 121]. These two facts lead to a completely different thermal coupling and thermal dynamics between
the poly-heater and the MOSFET, which can be seen from the characterization of the heating and cooling dynamics in Figure 3.31. was applied abruptly while
and
(proportional to
) were measured simultaneously.
was calculated by multiplication of
and
.
Although the switching of shows a very comparable time
evolution to the measurements on the fabricated wafers (Figure 3.30),
does not reach a thermal equilibrium
within 100 s. While the stabilization of
needs approximately 10 ms,
the stabilization of
needs 30 min at least. This
makes the calibration quite tedious and a pulse-like elevation of the temperature impossible because the whole system needs much longer to reach thermal equilibrium than the previously described poly-heater-device-chuck-system.
One way to overcome the challenge of slow heating and cooling dynamics would be to implement a control loop, e.g., using a proportional-integral-derivative (PID) controller illustrated in Figure 3.32. In this context, it is quite easy to implement one in order to hold , which is proportional to
, at a constant value by adjustment of
the control variable
according to the calculated difference
between the setpoint for
(
) and the measured process variable
=
. Unfortunately, this does not change the
behavior of
, which is proportional to
. As discussed in Figure 3.31,
stabilizes within 10 ms and is
constant afterwards while
drifts for a longer time. Thus, the
implementation of a controller in order to hold
at a constant value by adjustment of
seems to be the proper solution. In
such a controller,
corresponding to the set
would be the setpoint,
would be the control variable and
would be the process variable, which is
measured in order to calculate the error.
However, such a controller cannot be realized, since depends not only on
. In fact,
changes also due to device degradation.
If, for example,
was held constant during the stress
phase in eMSM measurements by adjustment of
,
would increase continuously because
degrades during stress. As a result,
would increase, which accelerates
again the degradation of the device. This could consequently overheat the device dramatically. During the recovery phase,
recovers, which would lead to a decrease
of
and thus to a cooling effect. As a
result, neither during stress nor during recovery,
could be held at a constant value by
adjustment of
without changing the degradation and
recovery state considerably.
Besides the difficulties associated with the thermal dynamics of the system, also difficulties related to the calibration of nano-scale devices made it nearly impossible to use the poly-heater system. Due to the fact that single oxide
defects cause RTN signals with steps of several pA up to µA, switches periodically around the
calibration point in any nano-scale device. If steps in the drain current of the same magnitude were caused by temperature changes, the corresponding temperature change would be several °C. Even if a nano-scale device is
suitable for calibration (no RTN signals), the elevated temperatures during the calibration often lead to the creation of new defects which change the
level. In other words, the calibration is
not reproducible. In this case, a lot of devices have to be calibrated in order to be able to calculate mean values for the calibration parameters.
From these experiences, it can be concluded that temperature accelerated measurements using an in situ poly-heater are advantageous in the term of the application of fast temperature ramps only if a defined temperature gradient can form between the heating wires and the thermo chuck. In the case of devices mounted on a ceramic package, the time until thermal equilibrium is reached is quite comparable for devices heated by a poly-heater and devices heated by a furnace.
In this chapter, an overview of commonly used techniques for the experimental characterization of degradation mechanisms is given and challenges which had to be faced for the measurements conducted in this thesis, are
discussed. In this context, two methods for the extraction of from single point
measurements in eMSM sequences are compared. It can be concluded that the extraction of
using a constant current
method and the extraction of
using a constant voltage
method are equivalent methods if three requirements are fulfilled: First, the
-
characteristics shift during stress and
measurement along the
-axis but do not change their slope and
curvature significantly. Second, the measurement current in the constant current method and the measurement voltage in the constant voltage method are chosen in the subthreshold region near to the threshold voltage of the
unstressed device. Third, the device-to-device variability is taken into account, which means that the recovery conditions are set individually for each device depending on its threshold voltage. In case that one of these requirements is
not met and depending on the stress and measurement conditions, the extracted
and
can even differ
more than 10%.
However, in measurements differences up to 100 % were observed at certain stress conditions. Due to the fact that the measurement setup for the constant current method has been developed for BTI measurements (
0 V) only, the stress voltages drift as soon as stress conditions with
0 V are applied. As a
consequence, the degradation state of the device using the constant voltage method and using the constant current method differ from each other significantly. This leads to completely incompatible
traces extracted from both
methods. The measurements presented in the following chapters were performed using the constant voltage method since the stress voltages are stable during stress.
Additionally, in order to accelerate the degradation and recovery of MOSFET parameters by the application of fast temperature ramps independently from each other, a hardware and software application for the temperature control of in situ poly-silicon heater structures has been developed. Measurements on the available devices, which are mounted on a ceramic package, showed that the heating dynamics differs significantly from the one introduced in previous studies because the thermal properties of the surrounding materials differ. As a conclusion, such setups for temperature accelerated measurements are advantageous in the term of the application of fast temperature ramps only if a defined temperature gradient can form between the heating wires and the thermo chuck. In the case of devices mounted on a ceramic package, the time until thermal equilibrium is reached is quite comparable for devices heated by a poly-heater and devices heated by a furnace, namely more than 30 min. As a consequence, the measurements presented in the following were performed at a constant temperature during stress and recovery.
It is widely accepted that discrete steps in the traces, which are caused by
individual oxide defects, can be experimentally resolved only in nano-scale devices (this is also discussed in Subsection 2.1.3 and shown in Figure 2.8). However, during the measurements conducted in this thesis discrete steps in the
traces were also measured in
large-area devices. An example is shown in Figure 4.1. In this figure an RTN signal measured on a large-area device with
10 µm and
120 nm is illustrated.
During the first observations of discrete steps in large-area devices, they were misinterpreted as contact issues. Especially in measurements directly on chip, a temporary failing contact between the needles and the pads have a
similar impact on traces as the discrete steps
associated with charge carrier exchange events caused by oxide defects. However, such steps were observed in a significant number of large-area pMOSFETs and their characteristic capture and emission
times showed a bias and a temperature dependence. In particular, 40 % of the large-area MOSFETs showed step heights of
0.15 mV, 30 % showed
step heights of
0.5 mV and 10 %
showed step heights of
1 mV. Since no studies on
discrete steps in
traces in large-area devices
have been reported in the literature up to now.
The step heights of discrete steps in the traces caused by individual
defects in nano-scale MOSFETs are exponentially distributed, as shown in Subsection 2.1.3. Since this empirically found distribution has
been formulated based on the measurements of numerous devices and hundreds of defects, it is assumed that the influence of device-to-device variation on the number of oxide defects and random dopants are considered. From the
CCDF in Equation 2.2 the probability that a step height with a value greater than a certain
occurs in a device with a
certain
and
can be calculated.
First the probability to measure a step in traces with
0.15 mV (smallest observed
in the large-area devices) in nano-scale devices with
160 nm and
120 nm is calculated. For this purpose,
pMOSFETs of a 130 nm commercial
technology with
2.2 nm were considered. With
F and the mean
value of the exponential step height distribution for nano-scale devices with the dimensions mentioned in this paragraph,
V (Equation 2.3), the probability is
.
By contrast, the probability to find a step with
0.15 mV in the
traces of large-area devices
with
10 µm,
120 nm as it was observed it is orders of magnitude smaller. With
F, the mean
value of the exponential step height distribution for large-area devices with the dimensions mentioned in this paragraph,
V, according to Equation 2.3 the probability is
.
These results show that it is quite likely to observe discrete steps in the traces of nano-scale devices
but it should be highly unlikely to observe them in the signal of large-area devices. However, in 40 % of the large-area MOSFETs step heights with
0.15 mV were measured which is
orders of magnitude more than the calculated probability.
In the introduction of this chapter, it is mentioned that the characteristic capture and emission times of the discrete steps in the traces of large-area devices
showed a bias and a temperature dependence. In this context, the experimental characterization of these dependencies is presented in the next section.
The fact that it is assumed to be highly unlikely to measure discrete steps in the traces caused by individual
defects leads to the assumption that maybe other processes are responsible for the observed discrete steps. For further conclusions, the temperature and bias dependences of the characteristic times of the RTN signal in Figure 4.1 were obtained. Therefore, pMOSFETs mounted on ceramic packages were measured since in
such an experimental setup contacting issues are minimized.
The experimental characterization of the steps in large-area devices appeared to be quite complicated. Most of the observed step heights are smaller than 0.5 mV, which is very close to the resolution limit of the setup. As soon as the noise amplitude of the signal increases slightly due to, e.g., previously applied stress or elevated temperatures the steps cannot be extracted from the trace anymore. Therefore, statistics cannot be captured with such a small sample set. Nevertheless, a large-area device RTN signal could be characterized, shown in Figure 4.1.
In this figure at least three RTN signals can be seen. The signal with the largest step height,
0.2 mV, was characterized since the others were not
accurately detectable over different temperatures and gate bias conditions. The results of this analysis is shown in Figure 4.2. The mean values of
and
were obtained according to
Equations 3.9 and 3.10, respectively. It is quite remarkable that
and
behave similarly to the
and
of an individual defect in a nano-scale device (see
Subsection 2.1.3): With increasing
,
decreases and
increases and both decrease with
increasing temperature.
Unfortunately, as mentioned previously, a thorough analysis of the “defect" parameters with the TDDS framework was not possible. As soon as a stress bias was applied the discrete steps could not be resolved anymore. This results in a too small data set in a too narrow gate bias region to check whether the four state NMP model can explain the observed behavior in order to make conclusions on the properties of such a “defect" in large-area devices. Nevertheless, a few thoughts which might be useful for a future work on this topic are summarized in the following.
• The large-area devices showing discrete steps in their traces in the shown
measurements have a small ratio
/
. They are quite short but very wide. So far, the dependence of the step height
distribution on the channel area or on
and
independently from each other have been made [18, 56]. However, any study on the
dependence of the exponential step height distribution on the
/
ratio has been found – especially for very small ratios. Thus, the empirically found
exponential step height distribution might have a different shape for different
/
ratios. In other contexts, e.g., the degradation and recovery of the device-to-device
variability, it has been discussed that the edge area might play a role for experimental characterization [123]. This is because, the oxide in the outer regions (edge area) grows less homogeneously than in the middle of the active area
during fabrication. Therefore, relative to the active area of the oxide, the edge area is larger in narrow long channel devices than in short wide channel devices. Although the edge area is not the reason for the discrete steps in the
measurements, it shows that
/
ratio related effects might have an impact on the step height distribution.
• The discrete steps in large-area devices were always measured in the subthreshold region. In this regime, the conductive channel is not completely formed. Thus, similar to the percolation path in nano-scale devices shown in
Figure 1.4, the current flow is not uniformly distributed over the width and single defects might have a similar impact on as shown for nano-scale devices.
• Possible causes for the steps in large-area devices might be capture and emission events of not a single defect but of a cluster of defects. If, for example, the capture and emission events of several defects are coupled and they
capture and emit charge carriers simultaneously, the step height in the trace would be of course
larger than step heights caused by single defects. With this idea, several questions arise, like if and how such clusters can form, if and how the capture and emission events can be coupled and many more.
In order to obtain the cause of discrete steps in large-area devices, a thorough experimental analysis is required. The analysis remains an open issue for future works.
About 40 % of the large-area MOSFETs showed step heights of
0.15 mV in
measurements,
30 % showed step heights of
0.5 mV and 10 %
showed step heights of
1 mV. Due to the challenging
experimental characterization of steps close to the resolution limit of the experimental setup, the bias dependence and the temperature dependence of only one RTN signal could be characterized. It was
observed that with increasing
,
decreases and
increases and both decrease with
increasing temperature. Such a behavior of the characteristic capture and emission times is comparable to the behavior of the characteristic times of single defects. However, due to a too small data set it could not be proved if
and
can be modeled with a four-state NMP model. Finally, a few thoughts on possible causes for such steps in
traces in large-area devices
were summarized. For example, not a single defect but a cluster of coupled defects might cause such steps. However, further analysis is required on this topic in order to give a proper explanation for possible causes.
BTI and HCD are among the most important reliability issues in modern devices. However, as already discussed in the previous chapters, these degradation
mechanisms are typically studied in idealized settings. In particular, for BTI studies no voltage is applied to the drain, leading to homogeneous conditions across the oxide and thus to a homogeneous
degradation. As soon as is increased, degradation becomes more and more
inhomogeneous and the contribution of HCD to the total degradation increases (see Subsection 2.3.1). Even though it is well understood that MOSFETs in real circuits are rarely subjected to idealized BTI or HCD conditions, there is only a limited number of studies available on the
impact of the mixed stress conditions as illustrated schematically in Figure 3.1. Therefore, a thorough experimental study of the impact of mixed stress conditions on
2.2 nm
pMOSFETs characteristics of a 130 nm
commercial technology (
−1.5 V and
465 mV) is presented in this chapter, which contains the first
experimental characterization at the single defect level.
As an introduction to this chapter, it should be again mentioned that the permanent component, on the one side, is attributed to the generation of interface and oxide defects, the hopping of through the oxide, and defects with large characteristic emission times. On the other
side, the recoverable component of degradation is typically attributed to the emission events of previously charged oxide defects within experimentally feasible time slots (on the order of seconds or minutes). In the following, the focus
lies mainly on the recoverable component of degradation.
The characterization of recovery in large-area devices (
10 µm,
120 nm or 130 nm) has revealed that with increasing
the recovery can be negligibly small. Figure 5.1 illustrates one measurement in this regard. In this measurement, seven cycles of 5 ks stress and 10 ks recovery at a constant
and each cycle
increasing
were performed.
was extracted from a single
point measurement of
at
(constant voltage
method introduced in Section 3.5). It can be seen that the threshold voltage shift during recovery (
), extracted according Equation 5.1 with
3 ms, reduces with
. For example, the
recovery trace after
−2.8 V (red trace) recovers less than 1 mV in
10 ks.
Figure 5.1: Recovery after mixed NBTI/HC stress: Seven cycles of 5 ks stress and 10 ks recovery
at a constant and increasing
were performed. Top: Recovery traces show
the reduction of
with
. Bottom: Com-
parison of
and a simulation using an electrostatic model. A discrepancy between
and
can be seen, especially at
−2 V.
can be negligibly small (less than 1 mV in 10 ks of recovery) after
mixed NBTI/HC stress. Figure source: [105].
threshold voltage shift | |
recovery time | |
lower limit of the experimental window during recovery | |
upper limit of the experimental window during recovery |
The measurement data are compared to a simulation using an electrostatic model as introduced in Subsection 2.3.1. This model takes into account a lateral position dependent
threshold voltage shift based on a linear approximation of the channel potential under stress according to Equation 2.54. This approximation is valid for lateral positions at the
inversion state. At the pinch-off, the channel potential can be calculated using Equation 2.55. In this regard, it is discussed in Subsection 2.3.1 that using an electrostatic model, it is expected that recovery is reduced after stress with increasing because drain-side defects most probably will not
contribute to recovery due to the reduced
. However, source-side defects should be
nearly unaffected by
and contribute to
independently from the drain bias.
Although an electrostatic model describes the behavior of after NBTI rather well, Figure 5.1 bottom shows discrepancies between the experimental data and the simulation after mixed NBTI/HC stress. The
measurements summarized in this figure, as well as measurements in [26], indicate that
can be negligibly small after mixed NBTI/HC stress. This would mean that almost no oxide defects contribute to the recoverable component. This contradicts the assumption that source-side defects contribute nearly unaffected to
. Since oxide defects are uniformly distributed all over the device area, such a behavior
cannot be explained by an inhomogeneous
only.
In order to analyze the origin of the discrepancies between the experimental data and the simulation, interplay between NBTI and HCD in large-area devices is
studied. For this, the eMSM measurement method was used according to Section 3.5 and extracted from a single point
measurement of
at
during recovery
(constant voltage method). 58 devices were measured at
130 °C using the following phases:
1. Measure: -
characteristics in the linear (
−0.1 V) and saturation regime (
).
2. Stress: application of a combination within the range of stress conditions
shown in Figure 3.1 per device:
is −1.5 V,
−2 V and −2.5 V,
is 0 V,
−0.5 V, −1 V, −1.5 V, −2 V, −2.5 V and −2.8 V for a certain stress time 0.02 s, 1.11 s and 1111 s.
3. Measure: for
3 ks at recovery conditions (typically
−0.1 V and
).
4. Measure: -
characteristics in the linear and
saturation regime.
From these measurements following was extracted:
• The threshold voltage shift directly after stress (): extracted
as
3 ms
.
• based on the
extraction for
different
.
• during recovery.
• The relative and
extracted from the
-
characteristics.
• Recovery according Equaton 5.1.
Figure 5.2: Degradation after stress: was extracted
at
3 ms. Top: For
20 ms the reduction of
across the gate oxide near the drain re-
gion suppresses NBTI with increasing
. For larger
it can be seen that with increasing
, the interplay between NBTI
and HCD leads to two local minima of
, at
−0.5 V and
−2 V. Center: Similar to the top panel. With increasing stress
time a drift minimum starts to form at
−0.5 V. Bottom: The minimum of
at
−0.5 V forms clearly for
11.1 s and
1.11 ks as discussed in [25, 26]. Figure source: [124].
From Figure 5.2 it can be seen that local degradation minima form after stress depending on the stress voltages and on the stress time. While after
20 ms
decreases or
stays constant with increasing
, for longer stress times
10 s a drift minimum forms
around
−0.5 V. Quite interestingly, for
−1.5 V a second minimum forms at
−2 V. The dependence of the formation of such minima on
is confirmed by the data of
Figure 5.4 for the two cases
−1.5 V and
−2.5 V. Especially for
−1.5 V it can be seen that if
100 s and
0 V,
is always lower than for homogeneous NBTI.
It has already been discussed in literature [25, 26] that drift minima such as shown in Figure 5.2 occur for long stress times. This behavior was explained by competing
processes contributing to the degradation: while sweeping from 0 V to,
e.g., −3 V,
reduces first
due to the fact that
decreases at the drain-side and, as a consequence
fewer drain-side defects capture charge carriers. From a certain
on, this effect is
compensated by the contribution of HCD to
which leads to
an increase. However, this behavior has not been observed for all
and
in the measurement. For example,
reduces at
−1.5 V and
20 ms with increasing
without forming any drift minima. It can be
concluded that whether and where a minimum forms in
depends
strongly on the stress time and on the gate and drain bias.
Figure 5.6: Degradation of the drain current in the linear and saturation regime: While the degradation behavior at
−1.5 V and
1.11 ks is comparable to the results in literature, the curves for
−1.5 V and
11.1 s show that
and
is higher for lower stress times
at certain
combinations. This means that the degradation evo-
lution of both turns around during stress. Similar behavior was also observed for the degradaton of
and
. Figure source: [124].
The analysis of the degradation of and
illustrated in Figure 5.6 shows a strong dependence on
as well. After
−1.5 V and
1.11 ks, a minimum in the
and
curves can be seen around
−1 V, which is comparable to the results in literature [25].
Remarkably, the measurements show that after shorter stress with
11.1 s
and
are higher at a certain
than after stress with
1.11 ks also at
−1.5 V. This means that with increasing stress time both first
increase, then this trend obviously turns around and they decrease again. Such a behavior has not been observed for higher gate bias
−2.5 V in these measurements. For a detailed analysis of the time
dependent
and
evolution at higher gate
stress bias, ten devices were measured using the MSM method (see Section 3.4) with the following phases:
1. Measure: -
characteristics in the linear (
−0.1 V) and saturation regime (
).
2. Stress: application of a combination per device:
is −0.7 V,
−1 V, −1.5 V, −2.0 V, −2.3 V and −2.8 V and
−2.8 V for a certain stress time.
3. Measure: -
characteristics in the linear and
saturation regime.
4. Repeat the second and the third phase with increasing .
5. Relax: application of recovery conditions for .
6. Measure: -
characteristics in the linear and
saturation region.
7. Repeat the fifth and the sixth phase with increasing .
Figure 5.7: Degradation and recovery of the drain current in the linear and in the saturation region as well as the threshold voltage shift: The degradation and recovery were
measured by short interrupts of the stress and recovery phase in order to measure and
. Especially
but also
show a local maximum after
one second of stress, a local minimum after approximately ten seconds of stress, and increases for larger stress times. No turn-around effect was measured for
.
From the -
characteristics
and
are extracted during stress
and recovery, which can be seen in Figure 5.7. It has to be noted that a small discrepancy occurs due to the interruptions of the stress and recovery phase compared to
measurements without interruptions (also mentioned in Section 3.4). This is because each interruption during stress leads to a partial recovery of the degradation and each
interruption during recovery slightly stresses the device. Therefore, the results from these measurements are shown as a schematic illustration but are not suitable as a basis for a further model development. The analysis of the
degradation and recovery of
and
shows that local minima
and maxima occur at higher gate bias as well. Depending on the stress voltage combination,
has a local maximum after
one second of stress, followed by a local minimum after approximately ten seconds of stress.
Such stress-time dependent turn-arounds of degradation have already been observed recently [99, 100, 102] and discussed in Subsection 2.2.6. Although the explanation in the
mentioned subsection cannot be applied to the measured turn-around in the same
way due to the different measurement methods, it gives an idea that II and the interplay of different types of defects together with the creation of secondary generated carriers triggered by II may determine the behavior of device degradation. However, these results merely suggest an interplay between NBTI and HCD and no
detailed information about the particular processes at the single defect level can be extracted from these measurements. Thus, the impact of mixed NBTI/HC stress on
the behavior of single defects was analyzed and the results are presented in the next subsection.
In addition to the large-area devices nano-scale devices are used to study the behavior of individual defects in greater detail. The capture and emission processes of single defects which contribute to recovery after NBTI stress, were analyzed. For this, 20 single defects in ten nano-scale pMOSFETs were measured and nine of them in four devices were fully characterized. A list of the
extracted defects can be seen in Table 5.1. These particular nine defects were selected in order to best represent the supposed uniform lateral distribution. They were also selected
according to their distribution in the spectral map and the ability to characterize properties like ,
, occupancy and step height over
a wide range of stress and recovery voltages.
Transistor | Def. Nr. | Def. Name | Type | ||
A | 1 | A1 | 0.40 | blue | |
2 | A2 | 0.21 | magenta | ||
3 | A3 | – | – | ||
4 | A4 | 0.32 | blue | ||
5 | A5 | 0.17 | magenta | ||
B | 1 | B1 | 0.71 | magenta | |
2 | B2 | 0.82 | green | ||
3 | B3 | – | – | ||
4 | B4 | – | – | ||
C | 1 | C1 | 0.81 | green | |
2 | C2 | – | – | ||
3 | C3 | 0.86 | magenta | ||
D | 1 | D1 | 0.20 | blue | |
Table 5.1: Relative lateral defect position and classification due to capture behavior: By exploiting the recovery drain bias dependence of the step heights for constant gate recovery
voltage , the lateral position
(0 at source, 1 at drain) was extracted [105]. The uncertainty of
is about 20 %. Defects A3, B3, B4 and C2 showed a very complex behav-
ior (e.g., due to an overlap with other defects in the spectral map at certain bias conditions) and were not characterized fully. The defects are assigned to three types according to their capture behavior during mixed NBTI/HC stress which is explained based on Figure 5.13.
For the characterization of the single defects, the TDDS framework described in Section 3.7 was used and following phases were applied:
1. Measure: -
characteristics.
2. Stress: Application of a combination within the region of stress conditions
shown in Figure 3.1 for a certain
.
3. Measure: at
and
for
.
4. Repeat the second and third phase times in order to capture the statistics.
The recovery traces contain the typical steps due to charge exchange events between the channel and the oxide caused by single oxide defects. Each defect causes exponentially distributed steps with a particular step height at a
particular mean value of . By assigning the unique steps to
a defect, the following parameters were extracted for each defect:
•
•
• Occupancy
• The lateral position
An analysis at the single defect level gives insight into the detailed behavior of individual defects already measured on average in large-area devices (Figure 5.1). The most
surprising finding is that some of the source-side defects do not contribute to after mixed NBTI/HC
stress although they do so after homogeneous NBTI stress with the same
. As discussed above,
this behavior cannot be explained by a simple electrostatic model only. In order to assign the behavior of a defect to its position, the relative lateral defect position
was extracted according to Equation 2.57 – the background is explained in Subsection 2.3.2 – by exploiting the readout drain bias dependence of the
step heights caused by the
defects (see Figure 5.8). In the present case
10 mV because
these were the largest step heights observed corresponding to defects in the middle of the channel. The results for the relative lateral positions are listed in Table 5.1 and shown in
Figure 5.9 as a schematic sketch.
Figure 5.8: Extraction of the lateral position: The lateral position (0 at source, 1 at drain) was extracted by exploiting the recovery drain bias dependence
of the step heights for constant
[104]. The subfigures
show the separation of the defects into three types according to their capture behavior during mixed NBTI/HC stress: blue group, green group and magenta group.
Measurement data and linear fits are labled with the defect name and the extracted relative lateral position. Figure source: [105].
In homogeneous NBTI measurements the defects show a typical behavior as discussed in Subsection 2.1.3. The emission behavior in
dependence of is shown in
Subfigure 5.10a for the device B. The emission times of the defects B1 and B2 at the readout conditions are within the experimental window. Therefore, as soon as B1 and B2
capture charge carriers during stress, the emission events are visible in the recovery trace as single steps. At
−1.6 V only defect B1 captures a charge carrier during stress because
10 s. Thus, emission events of B1 can be measured during recovery.
At
−2.2 V,
of B2 is low enough that it also
captures charge carriers within
10 s. Thus, in the recovery traces steps caused by B1 and B2 are
measured. In other words, by increasing
, the occupancy grows while
decreases. This behavior is also
shown in Subfigure 5.12a for all characterized defects.
The measurements at mixed NBTI/HC stress conditions illustrate a more complicated behavior. For a better understanding, it should be recalled what is discussed
in Subsection 2.3.1. For mixed NBTI/HC, it is expected that the occupancy of defects near the drain will be reduced
compared to homogeneous NBTI measurements due to the reduced and thus increased
. At the same time it is expected
that source-side defects remain almost unaffected at mixed stress conditions compared to NBTI conditions. However, Subfigure 5.10b reveals that
this assumption is not true. The defects A2 and A5, which are in the vicinity of the source, capture charge carriers at homogenous NBTI stress with
−1.8 V and emit them during recovery. Contrary to expectations, at
mixed NBTI/HC stress with
−1.8 V and
−2.8 V they do not emit charge carriers during recovery. This means
that their behavior is affected by
.
(a) NBTI stress measured on device B: The traces contain discrete steps caused by B1 and B2. Top: B2 does not capture a
charge carrier at
−1.6 V and thus does not emit during the recovery measurement.
Only one emission event of B1 can be observed here. Bottom: At
−2.2 V, B1 and B2 capture a charge carrier in 60 % and
50 % of the stress phase, respectively, and emit them during the recovery measurement.
(b) Mixed NBTI/HC stress measured on device A: The traces contain discrete steps caused by A1, A2,
A4 and A5. Top: At
−1.8 V and
0 V all four defects capture a charge carrier during stress and the
emission events can be observed in the recovery trace. Bottom: At
−1.8 V and
−2.8 V A2 and A5 do not capture a charge carrier and thus cannot
be observed in the recovery traces.
Figure 5.11: Recovery traces of nano-scale devices after different stress conditions: Six of 100 measured recovery traces show the behavior of the unique steps caused by single defects in the devices B and A. The percentage of emission events is not scaled directly proportional since only six of the 100 recorded traces are shown. Figure source: [105].
The behavior of all defects at mixed NBTI/HC stress conditions is shown in Subfigure 5.12b. At a fixed (around
−2 V) and increasing
the defects can be separated into three groups:
Either the occupancy is constant for the whole
range (defects A1, D1
and A4 – blue group) or it decreases continuously for
0 V (C1 and B2 – green group)
or it shows a local minimum at
−0.8 V, a local maximum at
−1.5 V and decreases to zero for
−1.5 V (C3, B1, A5 and A2 –
magenta group). The extracted
with respect to the drain bias
shows a slightly increasing trend only for the green group. For the magenta and blue groups
is either constant or
decreases.
The green and blue groups behave as expected and discussed previously. Drain-side defects (green group) show a decreasing occupancy and increasing for mixed NBTI/HC stress due to the significantly reduced
. Source-side to mid-channel defects
(blue group) show a constant occupancy over the whole
range. However, the
defects in the magenta group, where also the two interesting defects A2 and A5 are assigned to, show an unexpected behavior. This can be visualized by a parameterization in terms of
and
in Figure 5.13. This parametrization is illustrated in Figure 5.14 and shows that the traces for increasing
during NBTI stress
and increasing
at a fixed
during mixed NBTI/HC stress follow reverse trends for the green group. In other words, the occupancy increases and
decreases for increasing
while the occupancy decreases and
increases for increasing
. In stark contrast, the magenta group shows a
different behavior for increasing
. For these defects, increasing
causes a decrease in both, occupancy and
.
(a) NBTI stress: The defects show a typical behavior. By increasing the occupancy of the defects increases and
decreases.
(b) Mixed NBTI/HC stress: Three types of defects according to their occupancy behavior: blue, green and magenta.
Figure 5.13: Capture characteristics: For (a) NBTI stress and (b) mixed NBTI/HC stress. Figure source: [105]
The fact that A2 and A5 emit charge carriers after homogeneous NBTI but do not after mixed NBTI/HC stress does not mean that
they are volatile as soon as mixed NBTI/HC stress is applied. The volatility of all defects was checked regularly by intermittently applying homogeneous NBTI conditions. A volatile defect would have remained neutral after stress independently from the stress conditions. To the contrary, all defects which remained neutral after mixed NBTI/HC stress with high were found to be charged after these intermittent
homogeneous NBTI stress checks. None of the characterized defects showed a temporary electrical inactivity during the discussed measurements. The neutrality after mixed stress conditions must be
attributed to microscopic changes in the charge transfer process with increasing
. In this regard, Figure 5.15 shows that not only
can change but also
can change for different drain
biases. Consequently, the ratio
/
changes for some defects, which
affects the occupancy, illustrated in Figure 5.16. This means that as long as
and
at stress condition, the defect
captures a charge carrier during stress and emits it during recovery (top panels of Figure 5.17). However, if the relation is reversed
, the situation is more
complicated. Then, it is more likely that a defect emits a captured charge carrier immediately after the capture event while the stress bias is still applied (central panels of Figure 5.17).
Although the capture and emission events can repeat several times, it is very likely that no emission event can be measured at recovery conditions, which explains the considerable reduction in occupancy. By contrast, volatile defects
do not capture or emit charge carriers at all (bottom panels of Figure 5.17).
Figure 5.14: Occupancy versus capture time: A parameterization of and
demonstrates the differ-
ence between green and magenta type shown for three defects. Dashed lines: For NBTI stress the occupancy increases and
decreases for increasing
(corresponds to an increasing
). Solid lines: As soon as
is held at a constant value
and
0 V, the occupancy of the green
defects shows a reversed trend compared to NBTI. The occupancy decreases and
increases. This can be explained
by the reduction of
near the drain for
0 V. By contrast, the occupancy
of the magenta defects shows a completely different trend, namely towards decreasing
for a decreasing occupancy. This
is an indication for a different process. Figure source: [105].
It can be concluded that depending on their detailed configuration, defects at all lateral positions can remain neutral after mixed NBTI/HC stress and thus do not
contribute to . This is the primary reason for the discrepancy between the experimental data and
simulation at high
as shown in Figure 5.1. So far, such a behavior has not been considered in the current models because oxide defects have been studied only under homogeneous NBTI
conditions. In order to explain such a complex behavior like the distortion of the characteristics of source-side defects, also non-equilibrium carrier transport processes induced by the high
have to be taken into account in addition to an
inhomogeneous
.
Figure 5.16: Change of occupancy in respect of the ratio of emission to capture time: Shifts of and
by a few orders of magnitude af-
fect the occupancy. Top: Schematic visualization of the shift from
to
at stress conditions. Bottom:
Occupancy in respect to the ratio
/
is zero if
and at its maximum if
. Figure source: [124].
Figure 5.17: Schematic illustration of capture and emission events: The charge state of the defect 0 if it is neutral and 1 if it is charged. Top: at stress condition. The defect
captures a hole during stress and emits it during recovery. Center:
at stress condition. The defect
captures a charge carrier and emits it immediately afterwards at stress conditions. As a consequence, no emission event can be measured at recovery conditions. Bottom: Volatile defects are not electrically active.
In this context, the considerable change of and
can be explained by a change of
the transition rates
and
between the states
and
and the states
and
, respectively, in the four-state NMP model
(Figure 2.22) [125]. The calculation of the transition rates includes among other factors the energy distribution function of the charge carriers (discussed in
Subsection 2.1.5 and shown in Equations 2.22 and 2.24) illustrated in
Figure 5.19. This figure shows clearly that under homogeneous NBTI conditions the carriers in the channel near the source are in equilibrium and
thus properly described by the Fermi-Dirac distribution. As soon as a drain bias is applied this approximation is no longer valid. Carriers can gain energy by the channel field, exchange energy by various mechanisms, and can be
severely out of equilibrium.
Furthermore, if the device is operated near or beyond pinch-off conditions, carriers with sufficient kinetic energy can trigger II and consequently generate secondary carriers. As a consequence,
additionally to the minority charge carriers in the channel also majority charge carriers are available and may interact with the oxide defects. In Figure 5.19, this is shown as a change
of the distribution function of the electrons. Thus a thorough carrier transport treatment by means of a solution of the BTE for each combination and each lateral position is needed for
such situations.
Figure 5.19: Distribution function of holes and electrons in the vicinity of the source: Under homogeneous NBTI conditions (
−1.5 V) the carriers in the channel are in equilibrium and thus properly
described by the Fermi-Dirac distribution. By contrast, as soon as a drain bias is applied the carrier ensemble can be severely out of equilibrium. Furthermore, if the device is operated near or beyond pinch-off conditions carriers with
sufficient kinetic energy can trigger II and consequently generate secondary carriers. With a thorough carrier transport treatment by means of a solution of the BTE for
each
combination and under consideration of secondary
generated carriers the distribution functions for
0 V can significantly differ from
the equilibrium solution.
For this purpose, the quasi-equilibrium model, termed NMP, which approximates the carrier energy
distribution function by a Fermi-Dirac distribution independently from
is expanded to the
NMP
model, which includes the distribution
functions for holes and electrons evaluated with the higher-order spherical harmonics expansion simulator SPRING [125]. Thereby the bipolar BTE was solved self-consistently including phonon and
impurity scattering mechanisms as well as impact ionization with secondary carrier generation.
The NMP model implies that oxide defects mainly
interact with carriers in the valence band. Moreover, as it is discussed in Subsection 2.3.1, defects at the source-side are unaffected by
. In contrast, the
NMP
model considers the interaction of
high energetic carrier in the valence band as well as the interplay of defects with the secondary generated electrons in the conduction band. With this model, the observed defect behavior of
-dependent transition
rates even for defects located in the vicinity of the source contact can be captured quite well.
(a) Electric field: Lateral dependence of obtained from simulations with the
device simulator MINIMOS-NT.
(b) Carrier concentration: Lateral dependence of the carrier concentration obtained from simulations with MINIMOS-NT.
Figure 5.21: The lateral electric field and carrier concentration: For the simulation of the transition rates between the defect states and
and the states
and
of the four-state NMP model at different
.
By coupling the NMP model with the device simulator MINIMOS-NT [126] and by considering the real distribution functions of the holes and electrons, the accurate transition rates between the
states and
and the states
and
for different
can be calculated. Thus the behavior of
and
under different stress conditions
can be simulated. The electric field and the carrier concentration obtained in simulations using MINIMOS-NT are shown in Figure 5.21. After obtaining the NMP parameters of a defect based on the gate bias dependence of
and
(Figure 5.22 for the defect B1), the NMP parameters under consideration of the correct distribution function of the charge carriers in the channel the
and
behavior for different
can be calculated without introducing
any new parameters.
Figure 5.22: Gate bias dependence of the characteristic times of switching defect B1 modeled with the four-state NMP model: The left panel shows the measurement data (circles)
and the simulation results (solid lines). The right panels show the shift of the defect due to an increased (top) and the different capture and emis-
sion pathways which cause the switching behavior. The switching point describes the change from the preferred path for emission
to
. Charging the defects always proceeds over the
path
. Figure source: [125].
Figure 5.24 shows the difference between modeling the characteristic quantities of defect B1 using the NMP model and the NMP
model. The characteristic times
and
modeled using the NMP
model show an increasing trend simply
due to the change of
at this lateral position and at
−1.5 V. This does not correspond to the experimental data, which
shows a slightly decreasing trend. Furthermore, although the simulated occupancy captures the general decreasing trend for increasing
, it does not reflect the complex experimental
behavior. Only if the non-equilibrium conditions are correctly considered an agreement with experimental data is obtained. The NMP
model is able to capture the rather
complex experimental trends, like the decrease of the occupancy to zero at high drain voltages, and properly describes all characteristic quantities of B1.
(a) NMP model assuming equilibrium channel carriers: Neither and
nor the occupancy can be mod-
eled properly. The simulation data of
and
show an increasing trend due
to the change of
, which does not correspond to the
experemental trend.
(b) NMP model assuming non-equilibrium conditions: This model is able to capture the rather complex experimental trends, like the decrease of the occupancy to zero at high drain voltages, and properly describes all characteristic quantities of B1.
Figure 5.24: Experimental characterization of the defect B1 for increased drain voltage vs. simulation results obtained with the NMP model:
Top: and
for
−1.5 V and
−2.5 V. Center: Simulated occupancy for different
. Bottom: Occupancy at
2 s – simulation (dashed lines) and experimental data (open circles).
Figure source: [125].
The behavior shown in Figure 5.24 depends strongly on the configuration of the defect and its lateral position. The impact of the different distribution functions on the defect’s behavior cannot be formulated generally. From the experimental results, one can observe that defects assigned to the magenta group are more affected by changes in the distribution functions of the holes and electrons than defects assigned to the green or blue groups. However, the lateral position of a defect is not a meaningful measure for the classification of the three color groups. For example, the defects A5, D1 and A2 are located near the source and quite close to each other but only A5 and A2 show the typical behavior of the defects in the magenta group.
Using the NMP model, not only the behavior of
individual defects can be simulated with a excellent agreement with the experimental data, also the recoverable component of
of large-area devices can be
modeled. This can be done by assuming a large number of defects with different NMP parameters and by considering the lateral and bias dependent distribution functions of the charge carriers in the
channel. The recovery
of the measurements discussed in Section 5.1 can be modeled for different bias stress conditions. Figure 5.25 shows that as long as the carriers in the channel are assumed to be
in equilibrium independently of the drain bias,
is reduced only due to the change of
and no agreement between the
experimental data and the simulation can be obtained, quite similar to the discrepancy shown in Figure 5.1 using a simplified electrostatic model. Quite to the contrary, using the
non-equilibrium distribution function, the modeled
captures the experimental observations for different stress bias combinations very
well.
Figure 5.25: Recovery in large-area pMOSFETs: The open circles show the experimental data and the solid and dashed lines illustrate the simulated threshold voltage shifts.
Top: Comparison of simulation and experimental data for homogeneous BTI conditions. This data set was used to calibrate the NMP model to extract a unique
parameter set for all simulations. Bottom: after mixed stress conditions. The NMP
model (solid lines) captures the experi-
mental trend, while the equilibrium NMP model (dashed lines) fails to predict the recovery behavior. Figure source: [125].
Finally, Figure 5.26 highlights the main difference between the NMP model and the NMP
model based on the lateral
distribution of charged oxide defects directly after stress. Similar to the discussion in Subsection 2.3.1 and the illustration in Figure 2.36, without taking into account non-equilibrium effects defects located near the source remain unaffected. Their behavior does not depend on the drain bias. By contrast, defects
located near the source or in the middle of the channel may be uncharged after mixed NBTI/HCD stress due to the reduces oxide field. The NMP
model, which takes non-equilibrium
effects as discussed in the current chapter into account, predicts a faster reduction of charged defects with increasing drain bias. Remarkably, not only defects located near the drain but also near the source may remain uncharged,
which corresponds to the experimental observations.
Figure 5.26: Comparison of the distribution of charged oxide defects directly after stress in large-area pMOSFETs: Using the NMP model defects in the source region are
unaffected by an increased
. Defects located near the drain as well as
in the middle of the channel may remain uncharged due to the reduced oxide field. The NMP
model predicts a faster reduction of
charged defects (highlighted areas) with increasing drain bias. Remarkably, defects located near the source may remain uncharged as well, which corresponds to the experimental observations. Figure source: [125].
The term of defect volatility is introduced as transitions between active and inactive defect states in Subsection 2.1.6. Volatility describes the phenomenon that defects repeatedly disappear (become electrically inactive) and reappear (become electrically active) during measurements. In other words, a volatile defect does not capture or emit charge carriers, schematically shown in Figure 5.17 bottom. In the previous section, the results for the recovery after mixed NBTI/HC stress are presented and it is shown that recovery can be seriously reduced due to non-equilibrium processes. Even source-side defects can remain neutral after mixed NBTI/HC stress as shown schematically in the central panels of Figure 5.17. Although the neutrality of some defects after mixed NBTI/HC stress has the same consequence for recovery as volatile defects, namely no contribution to recovery, there is a fundamental difference between the neutral defects during recovery and volatile defects. Neutral defects affect only the recovery after mixed NBTI/HC stress but not recovery after homogeneous NBTI stress while the volatile defects disappear from all measurements and affect recovery after homogeneous NBTI stress as well. It is mentioned that the volatility of the characterized defects in the previous section was checked regularly by applying homogeneous NBTI conditions and measuring if the observed defects are still electrically active. None of them were volatile during the measurements presented in the previous section. However, following the termination of this study after thousands of cycles of mixed NBTI/HC stress, some defects simply disappeared from the homogeneous NBTI checks. This could be attributed to volatility and is discussed in this section.
(a) Cycles with only homogeneous NBTI stress: Ten cycles of 1 s NBTI stress/3 ks
recovery/1 s NBTI2 stress/3 ks recovery were performed at
125 °C. Top: Schematic sketch of the measurement
sequences. Center: recovery traces. Bottom:
defined according Equation 5.1 shows
a reduction of 3 %.
(b) Cycles of NBTI and mixed NBTI/HC stress: Eight cycles of
1 s NBTI stress/3 ks recovery/1 ks mixed NBTI/HC stress/1 ks recovery were performed at
125 °C. Top: Schematic sketch of the measurement
sequences. Center: recovery traces. Bottom:
defined according Equation 5.1 shows
a reduction of 22 %.
Figure 5.28: Recoverable component of homogeneous NBTI stress: Reduction of after NBTI due to a preceeding NBTI
stress (a) and reduction of
after NBTI recovery due to former mixed NBTI/HC stress (b).
In the following is extracted according to Equation 5.1, but with a different lower limit:
s
s
. One main difference to the previous section is,
that
in this section is the recovery after homogeneous NBTI
stress and not recovery in general.
Measurements on large-area devices shown in Figure 5.28 illustrate that the behavior of depends strongly on the “history" of the device.
is extracted from the recovery traces after homogenous NBTI stress with
−2.5 V,
1 s and
3 ks. In between measurements of
, stress and recovery cycles of different stress conditions were performed. For example,
the measurement shown in Subfigure 5.27a consists of the following alternating cycles applied subsequently to the same device: measurement of
, 1 s NBTI2 stress, 3 ks recovery, measurement of
, 1 s NBTI2 stress, 3 ks recovery and so on. In this context, NBTI2
stands for a homogeneous NBTI stress with a different gate bias than the one used for the measurement of
,
−1.6 V. From the bottom subfigure it can be seen that no
considerable reduction of
with respect to the cumulative NBTI2 stress time (
) can be seen. The reduction is
less than 0.5 mV in average at 125 °C, which corresponds to approximately 3 %. In this regard, it has been shown recently, that a considerable reduction of the recoverable component after alternating
homogeneous NBTI stress is measurable at higher temperatures and longer stress times [127–129]. For example, in [127],
shows a reduction of 25 % after 30 cycles of 10 ks
stress/10 ks recovery at 200 °C for a similar technology as it is used for the measurements.
By contrast, reduces significantly even at 125 °C if a mixed NBTI/HC stress has been applied previously, as shown in Subfigure 5.27b. The mixed NBTI/HC stress and recovery cycles were performed instead of the NBTI2 cycles.
,
and
of the mixed NBTI/HC stress and recovery were similar or the same as of the NBTI2 cycles but with a
−2.5 V applied. The measurement consists of the following
alternating cycles applied subsequently to the same device: measurement of
, 1 s mixed stress, 3 ks recovery, measurement of
, 1 s mixed stress, 3 ks recovery and so on. With respect to the
cumulative mixed NBTI/HC stress time (
)
reduces by 2.8 mV, which corresponds to 22 % at
125 °C. A quite similar reduction of
due to previously applied mixed NBTI/HC stress at the same temperature has been already observed [72].
It has been introduced previously that can be understood as the cumulative contribution of defects, which have been charged
during stress and emit charge carriers during the recovery phase. If
is reduced considerably, some of the defects must have disappeared in terms of
electrical activity and thus do no longer contribute to
. However, from the measurements on large-area devices the volatility of individual
defects cannot be observed because their individual contributions to the
traces cannot be resolved.
Therefore, the volatility checks performed on nano-scale devices (results presented in the previous section) can provide a detailed insight into the behavior of individual defects. The characterized defects in this regard are listed in
Table 5.2.
Similar to the measurement sequences shown in Subfigure 5.27b alternating homogeneous NBTI and mixed NBTI/HC stresses were performed on the nano-scale devices. The purpose of applying the homogeneous NBTI stress was comparable to the
one in the measurements on the large-area devices, the extraction of . Additionally, the activity of the observed individual defects was checked. In this
context, the measurements on device B as a representative device for all measured pMOSFETs are discussed.
Transistor | Def. Nr. | Def. Name | Volatility | ||
A | 1 | A1 | 0.40 | no | |
2 | A2 | 0.21 | no | ||
3 | A3 | – | no | ||
4 | A4 | 0.32 | no | ||
5 | A5 | 0.17 | no | ||
B | 1 | B1 | 0.71 | yes | |
2 | B2 | 0.82 | no | ||
3 | B3 | – | yes | ||
4 | B4 | – | yes | ||
C | 1 | C1 | 0.81 | yes | |
2 | C2 | – | yes | ||
3 | C3 | 0.86 | yes | ||
D | 1 | D1 | 0.20 | no | |
Table 5.2: Defect volatility after different stress conditions: Summary of the observed defect volatility. While the defects B3 and B4 showed a regular volatile behavior by getting inactive and active again from time to time, the defects B1, C1, C2 and C3 were volatile after all stress conditions.
Figure 5.29: Overall degradation and recovery after NBTI stress of device B: TDDS cycles with NBTI and mixed
NBTI/HC stress were recorded at
145 °C. Except of region
measurement cycles were performed like shown in Figure 5.27b top – NBTI stress / recovery / mixed NBTI/HC stress / recovery / ... Parameters obtained from NBTI measurements
are summarized here. Regions:
NBTI stress recovery cycles with
−2.2 V,
1 s and different recovery voltages
and
,
−1 V and different
,
−1.5 V and different
,
−2 V and different
,
different
and
,
cycles with
−2.5 V and
−2.7 V.
reduces because B1 and B2 change their step heights due to the former applied mixed
NBTI/HC stress. It was found that it is more likely for defects with larger step heights, which dominate
, to reduce. Furthermore, some defects like B1 become inactive and do not contribute to
anymore.
Figure 5.29 is a summary of all recovery measurements after homogeneous NBTI stress of device B. In this device, especially the defects B1 and
B2 were monitored. As can be seen, while increases with respect to the
cumulative stress time of the mixed NBTI/HC stress cycles 1–4,
reduces from 6.5 mV to 5 mV. After all mixed NBTI/HC stress cycles 1–5 (before baking)
has reduced to 2 mV. From the mean number of emissions (average over 100
traces of one measurement) and the step heights of the observed defect B1 and B2, the reasons for the reduction becomes clear: on the one hand, the number of emission events reduces, while on the other hand the step heights of the
defects change. In this particular case mainly the change of the step height of B1, which is the largest in this device, and the inactivity of B1 before baking contribute to the reduction of
. After three days of baking at 280 °C, B1 becomes active again, as shown
in cycle 6 in Figure 5.29, with a slightly different step height. During this last cycle, mixed NBTI/HC cycles was applied until the MOSFET failed completely.
Regarding the step height change during the cycles 1–4 in the particular case
shown in Figure 5.29, it has to be mentioned that both trends were measured in all devices, increasing and decreasing. In the small sample set, it appears that the decreasing
trend was more likely for defects with larger step heights, which dominate . This concerns B1, A1 and C1 listed in Table 5.1. Interestingly, according to the extraction of the lateral position in [104, 105, 124] these are the defects located laterally near the center of the oxide. Whether a defect changes its step height
during operation is predominatly due to deviations of the electrostatic surrounding of the defect as discussed in [16]. This means that as soon as other defects are generated/activated or annealed/deactivated in the vicinity of the
observed defect, the step height can change. Thus, the reduction of
due to step height changes is most probably attributed to activation or deactivation of
other defects near the observed defect in the oxide.
(a) Device B: The defect B1 is active in the unstressed device (top) and volatile after 1354.5 ks of different mixed NBTI/HC stress conditions (bottom).
(b) Device C: The defects C1, C2 and C3 are active in the unstressed device (top) and volatile after 270 ks of different mixed NBTI/HC stress conditions (bottom).
Figure 5.31: Spectral maps of devices B and C after NBTI stress: The spectral maps of the unstressed devices (top) shows that B1, C1, C2 and C3 are active after NBTI stress. After several cycles of mixed NBTI/HC stress B1, C1, C2 and C3 disappear completely from the spectral map. Especially in device C almost no defect contributes to recovery.
The dominant contribution to the reduction of after NBTI stress due to previous mixed NBTI/HC stress is the deactivation of defects, as can be seen in the spectral maps (extracted according to the method described in [40]) in Figure 5.31 for the devices B and C. Especially device C is remarkable in this regard because after 270 ks of mixed NBTI/HC stress all defects observed in this device disappear completely and do not reappear until the device failed completely. With this,
reduced permanently to zero. In this context, a few observations on the volatility of
defects in the introduced measurements can be summarized.
• Six out of 13 defects show volatility. Three of these six defects, B1, C1 and C3, are located laterally between the center and the drain. For the other three no extraction of their lateral position was possible due to their complicated behavior. While the statistics are small, it appears that it is more likely for defects near the drain to be deactivated with mixed NBTI/HC stress.
• In [58] the probability to find a defect showing volatility in a measurement window of several minutes to one day is estimated with 22 %. In the presented measurements 46 % show volatility in a measurement window up to 100 s, which is considerably more than this previous estimate. If the reaction barrier of the transition between active and inactive defect states is estimated with an Arrhenius law, as proposed in [65], the temperature plays a major role for the transition time constant and thus for the probability that a defect shows volatility or not. Despite the awareness that the estimation in [58] and the percentage found in the experiments are not fully comparable due to different definitions of the experimental window, self-heating effects might be an issue in the context of defect volatility.
• Apparently, there are two types of volatility. The defects B3 and B4, for example, repeatedly dis- and reappear as expected from volatile defects. By contrast, B1, C1, C2 and C3 disappeared after a certain cumulative stress time of mixed NBTI/HC stress and C1, C2 and C3 did not appear again anymore, even after baking and further measurements.
• It has been previously suggested that volatility concerns all oxide defects [65]. However, the continuous reduction of shown in Subfigure 5.27b as
well as the permanent deactivation of defects as shown in Subfigure 5.30b is an evidence that some defects are “permanently" annealed. The corresponding transitions to a precursor
state has been introduced recently in the context of the permanent component of NBTI degradation [74, 115]. Whether such transitions are truely “permanent" has to be checked in future long-term measurements.
In this chapter the impact of mixed NBTI/HC stress conditions on pMOSFET characteristics was studied with a focus
on the recoverable component of
degradation. It was found
that recovery of large-area devices after different stress conditions can clearly deviate from the behavior expected from a simple electrostatic model. This behavior is strong evidence that fewer defects contribute to recovery than
would have been expected. Interestingly, the study of the impact of mixed NBTI/HC stress on the behavior of single oxide defects showed that source-side defects can
remain neutral after mixed NBTI/HC stress and do not contribute to recovery although they are charged after homogeneous NBTI
stress. Defect characteristics like
and
distort and, as a result, if a
defect captures a charge carrier it emits it immediately afterwards still at stress conditions. Consequently, the defect remains neutral after mixed NBTI/HC stress. This
effect is determined by non-equilibrium processes triggered by hot carriers with sufficient energies and depends on the detailed defect configuration. By replacing the conventional equilibrium distribution in the charge trapping model
with a thorough carrier transport treatment which also considers secondary majority carriers in the channel, recovery after different stress condition can be modeled properly.
Furthermore, recovery after homogeneous NBTI stress depends on the “history" of the device. Especially if stress and recovery cycles with mixed NBTI/HC stress are performed, recovery after homogeneous NBTI stress is considerably reduced with respect to the cumulative mixed NBTI/HC stress time. Measurements at a single defect level show that this reduction is due to changes of the defect step heights, which is most probably attributed to a distortion of the electrostatic surrounding due to the activation or deactivation of other defects in the vicinity of the observed defect. On the other hand, with a much greater impact on the reduction of recovery, some defects simply disappear from the measurements after numerous cycles of mixed NBTI/HC stress. As a result, recovery after a subsequent homogeneous NBTI stress can be reduced down to zero. Such a deactivation of oxide defects has previously been attributed to defect volatility, a repeated dis- and reappearance of oxide defects. However, a continuous reduction of recovery as well as a seemingly “permanent" deactivation of some of the defects are evidence that a permanent deactivation might play a role here.
The results in this chapter show clearly that NBTI and HCD are not completely independent degradation mechanisms. The fact that effects like II, which are typically associated with HCD, affect the recoverable component of degradation, which is typically associated with the recoverable component of NBTI, leads to the conclusion that degradation mechanisms can be coupled.
The impact of mixed NBTI/HC stress conditions on SiON pMOSFET characteristics was studied with a focus on the recoverable component of degradation. It was found that recovery of
large-area devices after different stress conditions can clearly deviate from the behavior expected in a simple electrostatic model. This is a strong evidence that fewer defects contribute to recovery than would have been expected. In
this context, the study of the degradation behavior in large-area devices gives a hint that impact ionization and secondary generated carriers play an important role at mixed NBTI/HC conditions. However, from measurements of
large-area devices, the processes relevant for the recoverable component cannot be fully characterized. The study of the impact of mixed NBTI/HC stress on the behavior of single oxide defects showed that source-side defects can
remain neutral after mixed NBTI/HC stress and do not contribute to recovery although they are charged after homogeneous NBTI stress. Such a behavior cannot be explained by an electrostatic model only since the electrostatic
conditions at the source side are almost unaffected even at high
. The founding is that defect
characteristics like
and
distort and, as a result, if a defect
captures a charge carrier it emits it immediately afterwards still at stress conditions. Consequently, the defect remains neutral after mixed NBTI/HC stress. This effect is determined by non-equilibrium processes triggered by hot
carriers with sufficient energies and depends on the detailed defect configuration. With a model extension, including a thorough carrier transport treatment and under consideration of secondary majority carriers in the channel,
recovery after different stress conditions can be modeled properly.
Measurements show that recovery after homogeneous NBTI stress depends strongly on the “history" of the device. Especially if stress and recovery cycles with mixed NBTI/HC stress are performed, recovery after homogeneous NBTI stress is reduced continuously and considerably with respect to the cumulative mixed NBTI/HC stress time. Measurements at a single defect level show that this reduction is due to both, changes of the defects step height and deactivation of defects. The change of the step height is most probably attributed to a distortion of the electrostatic surrounding due to the activation or deactivation of other defects in the vicinity of the observed defect. With a much greater impact on the reduction of recovery, some defects simply disappear from the measurements after numerous cycles of mixed NBTI/HC stress. As a result, recovery after homogeneous NBTI stress can be reduced even to zero. Such a deactivation of oxide defects has been assumed to be attributed to defect volatility, a repeated dis- and reappearance of oxide defects. However, a continuous reduction of recovery as well as a seemingly “permanent" deactivation of some of the defects are evidence that a permanent deactivation might play a role here. For a full characterization of such a reduction of recovery, further long-term measurements of a large number of individual defects and a thorough analysis of self-heating effects are requried.
Boltzmann constant
elementary charge
temperature
thermo chuck temperature
device temperature
temperature minimum
poly-heater temperature
power dissipated in the
poly-heater
current flow through the
poly-heater
voltage applied to poly-heater
poly-heater resistance
thermal resistivity
threshold voltage
threshold voltage before
stress
channel area
effective channel area
drain current
on-resistance
bulk current
gate current
gate voltage
drain voltage
bulk voltage
drain
measurement voltage
linear drain current
linear drain current
shift
saturation drain current
saturation drain
current shift
charge pumping current
low level of the gate voltage
high level of the gate voltage
pulse amplitude
modulation amplitude
rise time
fall time
stress time
lower limit of the
experimental window during stress
upper limit of the
experimental window during stress
recovery time
lower limit of the
experimental window during recovery
upper limit of the
experimental window during revery
flatband voltage
interface-state density at
energy level E
interface-charge density
bulk-oxide-charge density
transconductance
maximum
transconductance
maximum
transconductance shift
threshold voltage
shift
threshold
voltage shift directly after stress
gate voltage at
stress conditions
gate voltage at
recovery conditions
gate voltage at
recovery conditions using the cv method
drain current at
recovery conditions using the cc method
supply voltage
drain voltage at
stress conditions
drain current
during stress
drain voltage at
recovery conditions
emission time
capture time
time
step height
threshold voltage shift during recovery
-
transfer characteristics
gate length
gate width
number of emission events
number of recovery traces
conduction band
Fermi level
intrinsic energy
oxide electric field
oxide thickness
oxide capacitance
sub-threshold slope
sub-threshold swing
sub-threshold swing shift
relative difference between
extracted from the cv method
and extrated from the cc method
relative permittivity
channel mobility
defect occupancy of the state
channel potential
lateral defect position
AER active energy region
BJT bipolar junction transistor
BTE Boltzmann transport equation
C-V capacitance-voltage
CCDF complementary cumulative distribution function
CET capture/emission time
CMOS complementary MOS
CP charge pumping
cv constant voltage
cc constant current
MOSFET metal-oxide-semiconductor field-effect transistor
FinFET multi-gate field-effect transistor
pMOSFET p-channel MOSFET
nMOSFET n-channel MOSFET
FET field-effect transistor
IGBT insulated-gate bipolar transistor
BTI bias temperature instability
NBTI negative bias temperature instability
PBTI positive bias temperature instability
HCD hot-carrier degradation
HC hot-carrier
HCI hot-carrier injection
OTF on-the-fly
MSM measure-stress-measure
eMSM extended measure-stress-measure
TDDS time-dependent defect spectroscopy
RTN random telegraph noise
SRH Shockley-Read-Hall
SILC stress induced leakage current
TDDB time-dependenc dielectric breakdown
NMP non-radiative-multiphonon
PDF probability density function
DFT density-functional-theory
II impact ionization
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The process of research and learning, which has led to this PhD thesis, was maybe the most challenging one in my life, associated with worries, doubts and sleepless nights as well as fun, delight and satisfaction. All throughout this emotional rollercoaster many people and institutions accompanied me. Therefore, I want to thank you all for your professional and emotional support.
• Prof. Tibor Grasser: As my PhD supervisor, you supported me during my research in a highly professional way. You stopped by my office frequently to ask how everything is going and your door was always open for me. From discussions with you, I learned to ask myself the right questions, which lead to interesting conclusions.
• Ben Kaczer and Hans Reisinger: As members of the international microelectronics community, both of you acted like supervisors to me. It was a pleasure to discuss relevant publications, characterization methods and research challenges. I want to thank you for the inspiring discussions and the help I received.
• Institute for Microelectronics: I had an enjoyable working environment. You are one of few institutes at TU Wien having the practice of a fair payment for PhD candidates (40 hours per week). Moreover, the members are well organized and everybody is engaged in administration and maintenance tasks. My sincere thanks for giving me the opportunity of working at this institute go especially to the former head of the institute, Prof. Erasmus Langer and the current head of the institute, Prof. Tibor Grasser.
• Michael Rathmair, Prof. Axel Jantsch and Friedrich Bauer: You played an important role for my research. By giving me the opportunity to measure on the probe station at the Institute of Computer Technology, I was able to finish my first successful measurements leading to interesting conclusions. Many thanks to all three of you for this enormously important possibility.
• My colleagues at the Institute for Microelectronics: You supported me in many different ways. The discussions, explanations, the free time we spent together and the emotional support were essential for finishing this thesis. I would like to thank you, Michael Waltl, for your very professional support regarding the experimental setup and characterization. Many thanks to you, Katja Puschkarsky, for the measurements we did together. Thank you, Stanislav Tyaginov and Markus Jech for the discussions. Especially thank you, Markus, for the modeling of the experimental data and your innovative and valuable ideas. Thank you, Markus, Alexander Grill and Yannick Wimmer for being also very good friends. Thank you, Manfred Katterbauer and Ewald Haslinger for the administrative support. Thanks to all members of the Institute for Microelectronics, who are not mentioned by name here.
• Fachschaft Doktorat: As the official representation of early-stage researchers you were an anchor during my PhD. Not only the political discussions regarding academia in general but also the networking with PhD candidates of other fields than mine were valuable to me for many different reasons. One of the most important things was to recognize that you are not alone. Almost every early-stage researcher faces similar challenges. This finding was an enormous motivation.
• My family, my partner and my friends: The emotional support I received from you all was irreplaceable and highly important for my mental health. I warmly thank you, the Ullmanns, for supporting me in any decision of my life and standing behind me. Thank you, Joachim, for being my friend and companion and for cheering me up in every situation, however difficult for me and us. I thank you, the Rosa group, for being my best friends.
Finally, I would like to finish with a quote, which highly motivated me during my work. In Momo by Michael Ende Beppo Roadsweeper says to Momo:
“Sometimes, when you’ve a very long street ahead of you, you think how terribly long it is and feel sure you’ll never get it swept. And then you start to hurry. You work faster and faster and every time you look up there seems to be just as much left to sweep as before, and you try even harder, and you panic, and in the end you’re out of breath and have to stop – and still the street stretches away in front of you. That’s not the way to do it.
You must never think of the whole street at once, understand? You must only concentrate on the next step, the next breath, the next stroke of the broom, and the next, and the next. Nothing else.
That way you enjoy your work, which is important, because then you make a good job of it. And that’s how it ought to be.
And all at once, before you know it, you find you’ve swept the whole street clean, bit by bit.
What’s more, you aren’t out of breath. That’s important, too."
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