6.5 BiCS Memory Hole Etching

The etching of the BiCS memory hole is a combination of the SiO and Si etching processes presented in Section 5.2. The initial structure which is to be etched is shown in Figure 6.20a. The width of the mask opening is 58nm, while the heights of the interchanging silicon and silicon dioxide layers are 50nm and 33nm, respectively. The silicon dioxide layer is etched using the model described in Section 5.2.1 and the silicon layer is etched with the model from Section 5.2.2 with the parameters listed in [113] and [11], respectively. Figure 6.20b shows the final topography after the sequence of processing steps are applied. The fluxes used for silicon etching are $\textrm{\ensuremath{F_{Br}}=2.5}\times\textrm{10}^{\textrm{18}}\textrm{s}^{\textrm{-1}}\textrm{cm}^{\textrm{-1}}$ , $\textrm{\ensuremath{F_{O}}=1.0}\times\textrm{10}^{\textrm{17}}\textrm{s}^{\textrm{-1}}\textrm{cm}^{\textrm{-1}}$ , and $\textrm{\ensuremath{F_{ion}}=1.0}\times\textrm{10}^{\textrm{16}}\textrm{s}^{\textrm{-1}}\textrm{cm}^{\textrm{-1}}$ . The fluxes used in the simulation of silicon dioxide etching are are $\textrm{\ensuremath{F_{e}}=2.5}\times\textrm{10}^{\textrm{17}}\textrm{s}^{\textrm{-1}}\textrm{cm}^{\textrm{-1}}$ , $\textrm{\ensuremath{F_{p}}=1.0}\times\textrm{10}^{\textrm{17}}\textrm{s}^{\textrm{-1}}\textrm{cm}^{\textrm{-1}}$ , and $\textrm{\ensuremath{F_{i}}=5.6}\times\textrm{10}^{\textrm{16}}\textrm{s}^{\textrm{-1}}\textrm{cm}^{\textrm{-1}}$ . The silicon and silicon dioxide were etched for 60s and 6s, respectively.

Figure 6.20: The initial and final topographies after applying Si and SiO

etching models for the fabrication of BiCS memory holes.

$\includegraphics[width=0.48\linewidth]{chapter_applications/figures/Initial_run2.eps}$	$\includegraphics[width=0.48\linewidth]{chapter_applications/figures/Final_run2.eps}$
(a) Initial topography	(b) Topography after etching

L. Filipovic: Topography Simulation of Novel Processing Techniques