5.1.4 Hot-Carrier Tunneling in MOS Transistors

It has been shown in Section 3.3 that the distribution function in the channel of a turned-on MOS transistor heavily deviates from the shape implied by a FERMI-DIRAC or MAXWELLian distribution. A model for the non-MAXWELLian shape of the distribution function was presented which accurately reproduced the carrier energy distribution along the channel.

To check the impact of this wrong high-energy behavior, the integrand of the TSU-ESAKI formula, namely the expression $TC({\mathcal{E}}) N({\mathcal{E}})$ has been evaluated for a standard device, as shown in the left part of Fig. 5.16, and compared to results. The simulated device had a gate length of 100nm and a gate dielectric thickness of 3nm. While at low energies the difference between the non-MAXWELLian distribution function (3.28) and the heated MAXWELLian distribution (3.24) seems to be negligible, the amount of overestimation of the incremental gate current density for the heated MAXWELLian distribution reaches several orders of magnitude at 1eV and peaks when the electron energy exceeds the barrier height. This spurious effect is clearly more pronounced for points at the drain end of the channel where the electron temperature is high. The non-MAXWELLian shape of the distribution function, indicated by the full line, reproduces the results very well.

The region of high electron temperature is confined to only a small area near the drain contact, as shown in the right part of Fig. 5.16, where the gate current density along the channel is compared to results. At the point of the peak electron temperature, which is located at approximately $x=0.8\ensuremath {L_\mathrm{g}}$, the heated MAXWELLian approximation overestimates the gate current density by a factor of almost $10^6$. It will therefore have a large impact on the total gate current density. The cold MAXWELLian approximation underestimates the gate current density in this region, while the non-MAXWELL ian distribution correctly reproduces the results.

Figure 5.16: Integrand of TSU-ESAKI's equation (left) and gate current density along the channel (right) of a MOSFET with 100 nm gate length and 3 nm gate dielectric thickness.

The non-MAXWELLian shape yields excellent agreement, while the heated MAXWELLian approximation substantially overestimates the gate current density especially near the drain region. Instead of the heated MAXWELLian distribution it appears to be better to use a cold MAXWELLian distribution in that regime since it leads to a comparably low underestimation of the gate current density.

The effect of hot-carrier tunneling on the total gate current of the devices is shown in Fig. 5.17. In the left part of this figure the gate current density for a 0.5$\,\mu$m turned-on MOSFET with a dielectric thickness of 4nm is shown as a function of the gate bias. Results from simulations are also shown in this figure. For low gate voltages ( $V_\mathrm{GS}$$<$ $V_\mathrm{DS}$) the peak electric field in the channel increases with increasing gate bias. The electron temperature is high and the heated MAXWELLian approximation massively overestimates the total gate current. If the gate bias exceeds the drain-source voltage, however, the peak electric field in the channel is reduced [258]. Therefore, for $\ensuremath{V_\mathrm{GS}}>\ensuremath{V_\mathrm{DS}}$ the electron temperature reduces with increasing gate bias and the heated MAXWELLian approximation delivers correct results. The non-MAXWELLian model (3.28) delivers correct results for all gate voltages.

The question remains if the hot-carrier tunneling current strongly depends on the gate length of the device. In the right part of Fig. 5.17 the gate current is given as a function of the gate length for different gate dielectric thicknesses (2.2nm - 3.0nm). Again, simulation results are used as reference. It can be seen that the heated MAXWELLian distribution delivers correct results only for large gate lengths, while it totally fails for smaller devices. The use of a cold MAXWELLian distribution, on the other hand, underestimates the gate current only slightly and seems to be the better choice if accurate modeling of the device physics is not that important or only a quick estimation is asked for. The non-MAXWELLian model correctly reproduces the results for all gate lengths and gate dielectric thicknesses.

Figure 5.17: Gate current for different values of the gate bias (left). Dependency of the total gate current on the gate length (right).

A. Gehring: Simulation of Tunneling in Semiconductor Devices