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Choosing the highlighted material parameters from Table 5.1 the
gate current density can be computed as a function of the gate bias. It is
commonly assumed that an underlying layer of SiO cannot be avoided -- or
is even deliberately introduced to achieve a lower trap density at the
interface to silicon. Thus, an underlying SiO
layer with a thickness of
0.5nm was assumed. The thickness of the high-
layer was adjusted so that
the effective oxide thickness (EOT) remains unchanged at 1nm. The gate
current density is shown in the left part of Fig. 5.21 as a
function of the gate bias for different material combinations. The commonly
assumed limit of 1Acm
gate leakage is also indicated. Both SiO
and
Si
N
show a much too high leakage, while Ta
O
, ZrO
, and HfO
stay below
1Acm
at
=1V. Due to the low conduction band offset, TiO
shows
an especially pronounced current increase for positive gate bias.
To assess the material parameters necessary to reach a specific maximum gate
current density the gate current has been calculated as a function of the
conduction band offset and dielectric permittivity as shown in the right part
of Fig. 5.21. Since it is often not possible to vary the
thickness of the underlying SiO layer it was again fixed at 0.5nm and the
high-
thickness was adjusted to reach an EOT of 1.5nm. The gate current
density was evaluated at a fixed bias point of
=1.5V and
=0V. The
current density decreases strongly with increasing conduction band
offset. Increasing the value of the dielectric permittivity
also
strongly reduces the leakage current due to the higher physical stack
thickness. However, materials with a conduction band offset below 1eV never
reach acceptable gate current densities.
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It may be asked which thickness of the high- layer is necessary to achieve
a certain gate current density. In the left part of Fig. 5.22 the
gate current density is shown for an effective oxide thickness ranging from
0.5nm to 2.0nm as a function of the high-
layer thickness. Again, the
stack consists of an underlying 0.5nm layer of SiO
and the simulations are
performed at a fixed bias point of
=1.5V and
=0V. In this plot
the curves are only drawn for an EOT of 0.5nm - 2.0nm, and conduction
band offsets of
eV to
eV have been considered. For a
conduction band offset of 1eV, large high-
thicknesses are necessary to
reduce the leakage. Such large stacks may pose problems due to fringing fields
from the drain contact which reduce the threshold voltage of the device.
The tradeoff between the dielectric permittivity and the conduction band
offset gives rise to further effects as shown in the right part of
Fig. 5.22. If the EOT has to be held at a fixed value, an increase of
the SiO layer thickness causes a reduced thickness of the high-
layer.
This is shown for different values of the permittivity (
-
). So, the total stack thickness may be larger than 8nm for
, or as small as 1.5nm if only SiO
is used. Such a reduction
of the total stack thickness, however, has no clear effect on the leakage. It
may cause the gate current density at a specific bias point to stay constant,
increase, or even decrease depending on the material parameters. For example,
the gate leakage for a material with
and a conduction band offset
of 1eV shows the maximum leakage at a SiO
layer thickness of
approximately 0.8nm. Therefore, a clear statement about the optimum
thickness of the interface layer obviously depends on the material parameters.
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A. Gehring: Simulation of Tunneling in Semiconductor Devices