5.1.6 Trap-Assisted Tunneling in ZrO Dielectrics

Since ZrO

offers good material parameters, it was further investigated by means of experiments and numerous results were published [264,265]. ZrO

pMOS capacitors have been fabricated by MOCVD (metal-organic chemical vapor deposition) on p-type (100) silicon wafers with an acceptor doping of 1.5e18 cm-3 and Al gate electrodes [265]. The overall thicknesses of the dielectric layers have been evaluated by spectroscopic ellipsometry. Employing a dielectric permittivity of the high- $\kappa$ material of $\kappa / \kappa _0$ =18, which has been found for thicker films, the comparison of optical measurements and the results of CV characterization implicates the presence of an interfacial layer with a permittivity in the range of 4 to 8. Table 5.2 summarizes the thicknesses of the high- $\kappa$ films and interfacial layers. Also given is the effective oxide thickness EOT. The values $\ensuremath {t_\mathrm{int}}$ and $\ensuremath {t_{\mathrm{high-}\kappa}}$ denote the thicknesses of the interface and the high- $\kappa$ layer.

Table 5.2: Layer thicknesses and EOT of MOCVD-deposited ZrO

layers in nm, after HARASEK [265].

Layer thickness	$\ensuremath {t_\mathrm{int}}$	$\ensuremath {t_{\mathrm{high-}\kappa}}$	EOT
6.9	0.75 - 2.0	6.15 - 4.9	2.0
12.7	0.3 - 1.0	12.4 - 11.7	3.0

10000

In the left part of Fig. 5.23 the measured gate current is shown for the two dielectric layers with the approximate shape of the energy barrier sketched in the insets. As reference the figure also shows the gate current for a 2nm and a 3nm SiO

layer (dotted lines). As expected, the measured current density is lower than for the SiO

counterparts. However, the TSU-ESAKI model cannot reproduce the measurements as it yields tunneling currents orders of magnitude lower than the measurements. This indicates the presence of strong trap-assisted tunneling due to a high trap concentration in the dielectric layer. By assuming a FRENKEL-POOLE like conduction through the dielectric layer the measurements could be reproduced (full lines). Note that in previous studies [264] tunneling through ZrO

layers fabricated by magnetron sputtering could be reproduced without considering trap-assisted tunneling. That indicates the presence of a high trap concentration due to the MOCVD process, in contrast to the sputtering process.

To clarify the trap energy level and concentration, the step response of the MOS capacitors has been measured as shown in the right part of Fig. 5.23 for the 12.7nm ZrO

layer annealed in reducing conditions (forming gas) and the 6.9nm layer annealed under oxidizing conditions. The gate voltage is turned off after being fixed at a value of 2.5V and the resulting gate current is measured over time. The transient gate current exceeds the static gate current by orders of magnitude and decays very slowly. This behavior can be explained assuming defects in the dielectric layer [266]. Using the trap-assisted tunneling model outlined in Section 3.8.2, a trap energy level of 1.3eV below the ZrO

conduction band edge, a trap concentration of 4.5e18 cm-3 and an energy loss of 1.5eV have been found. For the dielectric layer annealed under oxidizing conditions a trap concentration of 4e17 cm-3 was found.

To predict the performance of devices based on ZrO

dielectrics a well-tempered MOSFET as described in [267] with an effective channel length of 50nm has been simulated. EOT thicknesses of 2nm and 3nm SiO

and respective ZrO

layers have been considered. The left part of Fig. 5.24 depicts the conduction band edge in the channel for different gate-source voltages. It can be seen that the barrier is slightly lower for the ZrO

layer at $V_\mathrm{GS}$ =1.2V, while it is strongly reduced at $V_\mathrm{GS}$ =0.1V, which is due to the pronounced fringing fields from the drain contact.

An additional topic of interest for high- $\kappa$ dielectrics is the influence of trapped charges in the high- $\kappa$ layer on the threshold voltage of the device. The trap concentration in the ZrO

layer was increased from 1e15 cm-3 to 1e19 cm-3 with full trap occupancy in the dielectric layer. It can be seen in the right part of Fig. 5.24 that the threshold voltage strongly increases with rising trap concentration. This effect is therefore contrary to the decrease of the threshold voltage due to fringing fields described above.

**Figure 5.23:** Stationary (left) and transient (right) gate current measurements of the ZrO layers performed by HARASEK [265], compared with simulations.
$\includegraphics[width=.45\linewidth]{figures/IgVgInsets}$ $\includegraphics[width=.48\linewidth]{figures/decayFig}$

**Figure 5.24:** Well-tempered MOSFET conduction band edge along the channel for SiO and ZrO dielectrics (left). Influence of the dielectric trap concentration on the MOSFET threshold voltage (right).
$\includegraphics[width=.48\linewidth]{figures/conductionBand}$ $\includegraphics[width=.48\linewidth]{figures/thresholdVoltage}$


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