2.2.4 Gate Dielectric

According to the scaling theory outlined in Section 2.1, the gate dielectric thickness must shrink with every new device generation, reaching values of 2.2nm, 1.9nm, and 1.4nm for 180nm, 150nm, and 100nm gate length devices [23]. However, the quantum-mechanical tunneling effect comes into play if the energy barrier between gate and semiconductor becomes to small. One remedy against this effect is to use dielectric materials which have a higher dielectric permittivity. These materials allow to achieve a high physical thickness together with a small effective oxide thickness (EOT). The EOT is defined as the thickness of a SiO layer with equal capacitance. For a layer of SiO and a high- $\kappa$ dielectric, the EOT is

$\displaystyle \mathrm{EOT} = \ensuremath {t_\mathrm{sio_2}}+ \ensuremath {t_{\m... ...nsuremath{\kappa_\mathrm{sio2}}}{\ensuremath{\kappa_{\mathrm{high-}\kappa}}}\ ,$

where $\ensuremath {t_\mathrm{sio_2}}$ and $\ensuremath {t_{\mathrm{high-}\kappa}}$ denote the thickness of the SiO

and high- $\kappa$ layer, and $\ensuremath{\kappa_\mathrm{sio2}}$ and $\ensuremath{\kappa_{\mathrm{high-}\kappa}}$ are the respective permittivities. With high- $\kappa$ dielectrics it is possible to retain good control over the inversion charge even with physically thick dielectrics to block tunneling currents. This topic will be investigated in more detail in Section 5.1.5.

However, the gate dielectric reliability is a crucial issue, in particular with new materials. The parasitic tunneling current which flows through the dielectric gives rise to wear-out which means that the blocking capability of the dielectric is reduced, and even dielectric breakdown which is a sudden conductance increase. It is commonly assumed that this breakdown is caused by the gradual buildup of defects in the dielectric layer which may be caused by anode hole injection or the release of hydrogen from the Si-SiO interface [24]. This is especially critical for high- $\kappa$ dielectrics which do not form a native layer on silicon.

A. Gehring: Simulation of Tunneling in Semiconductor Devices


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