4.2.2 Stacked Segment Tunneling

As outlined in Section 2 advanced CMOS devices apply stacks of alternative dielectric materials and silicon dioxide to achieve a large physical, but small electrical thickness of gate dielectrics. Furthermore, non-volatile memories rely on stacked gate dielectrics to achieve asymmetry between the on- and off-state (see Section 5.2.2.3). Tunneling through such dielectric stacks requires models such as the numerical WKB method, the transfer-matrix method, or the QTBM, since the energy barrier has a non-linear shape.

MINIMOS-NT allows the definition of rectangular dielectric stacks consisting of an arbitrary number of independent segments, as shown in Fig. 4.3 (see also the user interface in Appendix D). The tunneling model, however, must only be evaluated once. Therefore, the segment with the highest index in the stack is chosen as master segment. As in the single-segment case, a reference and an opposite boundary is assigned to the stack. Only at these boundaries, the neighbor quantities are transferred to the master segment.

Further quantities which are necessary for tunneling, such as the conduction and valence band edge, the distance from the reference boundary, or the trap concentration, are transferred from each stack member segment to the master segment. A two-dimensional array is built up which describes the quantities in the whole stack region. In the master segment finally the chosen tunneling current model is evaluated and the calculated tunneling current is transferred back to the boundary node and partner node located at the reference and opposite boundary. There it is added to the continuity equation of the neighboring segments or to the contact current in case of metal contacts as described above.

Figure 4.3: A stack consisting of five segments. The neighbor quantities are transferred from the outer stack reference and opposite segment to the master segment. Furthermore, the energy barrier, distance, trap concentration, trap charge state, and trap occupancy is transferred from each stack member segment to the master segment.
\includegraphics[width=.9\linewidth]{figures/stack}

A. Gehring: Simulation of Tunneling in Semiconductor Devices