Since almost all available measurements of gate leakage in MOS devices are
performed on turned-off MOS transistors, a comparison with measurements will
be given before turned-on devices are investigated in
Section 5.1.4. The TSU-ESAKI model with an analytical WKB
transmission coefficient is in good agreement with recently reported data for
devices with different gate lengths and bulk doping [249,96] as
shown in Fig. 5.10 for nMOS (left) and pMOS devices
(right) [255]. It can be seen that the gate current density can be
reproduced over a wide range of dielectric thicknesses with a single set of
physical parameters. Additional measurements have been performed on MOSFETs
with a gate dielectric thickness of 1.5nm (see the lower part of
Fig. 5.10) and compared with the results of other simulators
(UTQUANT [256] and
MEDICI [257]). Under inversion condition the fit is not
perfect while under accumulation the measurements can be reproduced well. Note
that with UTQUANT, the low-bias tunneling current cannot be
reproduced and MEDICI completely failed for the pMOS device.
|
A. Gehring: Simulation of Tunneling in Semiconductor Devices