3.5.4 Interface Traps Build-up in -Channel LDD MOSFETs

Traps build-up while stressing LDD MOSFETs at a maximum substrate current is analyzed in this section by using charge pumping.

It is important to distinguish between two effects in considering the evolution of the degradation processes: (1) the evolution of the absolute damage (generated interface trap density and/or total charge trapped in the oxide) and (2) the influence of the damaged region on the device electrical characteristics.

It is known that the stressing of conventional -channel MOSFETs at bias which corresponds approximately to the condition of the maximum substrate current , results in a maximum creation of interface states in comparison with other gate biases [194]. The generation of interface traps is also predominantly responsible for the degradation of device static characteristics, such as the threshold voltage shift , drain current change and transconductance change , after stress at . The interface trap creation obeys a power-law relationship in time with a slope of on a double logarithmic scale in a wide range of stressing conditions, as confirmed by the charge-pumping measurements [194][30]. Whether and change in time with the same exponent in the power-law relationships as the changes, depends on presence of other degradation mechanisms [194], like the oxide charge build-up which proceeds with an exponent [104]. For stress at maximum , the degradation and also show an exponent , as found in several experiments [459][458][217].

In -channel LDD devices, the stress at results in a deviation from a simple power-law relationship. A saturation of on the log-log scale is reported for long stress times [499][183]. The saturation is explained in [499] by pushing the peak of the lateral electric field towards the drain while stressing, due to the electrostatic influence of the generated acceptor-like interface traps. Because of a reduced electric field and thereby, lower injection currents the interface states are generated at a lower rate. In addition, they are produced deeper in the LDD region where their influence on the device characteristics is smaller. A second explanation for the saturation of the characteristics involves a feedback effect of the generated acceptor-like traps. An increasing trap density decreases the local Fermi level at the interface due to the negative interface charge and leads to a lower occupation of the interface traps [183]. Because they are lower occupied they influence the drain current less. In addition, a high density of acceptor-like interface traps increases the hole-attractive normal field (Figure 3.23). Consequently, the hole injection current can increase, leading to an increased rate of the interface state creation. This effect has not been reported in literature.

Note that a similar disagreement exists in literature between the models for the degradation of conventional -channel MOSFETs. The characteristics of those devices also shows a deviation from the power-law relationship and a saturation for long stressing times. In one model, the region in which all traps become filled by injected electrons moves logarithmically in time towards the channel, whereas the electric field and the injection current remain unchanged during the stress [500][42][39]. In another model, the negative charge in the oxide due to trapped electrons reduces the injected electron current, thereby reducing the rate of oxide charge build-up [493][106][29]. The trapping itself occurs at the same place without saturation [480]. After charge-pumping studies in [30] it seems that both processes occur: a logarithmic spreading of the trapped region in time and a continuous logarithmic build-up of the trapped charge in time without saturation at particular positions.

The LDD -channel MOSFET used in this study is the same as the device analyzed in Section 3.5.3. MOSFET is stressed at and (). The evolution of the measured differential charge-pumping characteristics is presented in Figure 3.47. Using the constant amplitude method, discussed in Section 3.5.2, we extracted the spatial trap distributions from . The applied relation is shown in Figure 3.43. Figure 3.46 presents the calculated trap distributions at different stress times.

The distributions from the channel region to the coordinate of have been directly calculated from the curves in the interval , Figure 3.47. The trap distributions from to are obtained by fitting the experimental curves in the region . Remember that we have already analyzed the contribution to the characteristics from the particular areas in this LDD device in Section 3.5.3. The interval from the channel until corresponds to the region . In this region the trap distributions are less dependent on the uncertainty in the lateral doping profile and the local oxide thickness. As opposed, the part of the distributions from towards the drain is very sensitive to the device parameters involved at the gate-corner/LDD-region field fringing, like the LDD surface dopant concentration, oxide thickness and the geometry of the gate corner (Appendix E). We further assume that the stress-generated traps are acceptor-like and uniformly distributed in the forbidden band. Assuming the calculated spatial trap distributions to be superposed on the uniform trap distribution in the virgin device the charge-pumping characteristics are calculated by using the rigorous two-dimensional transient model. The differential characteristics shown in Figure 3.47 follow after subtracting the calculated from in the virgin device. The calculated curves agree well with the experimental data in the interval , which confirms a reasonable accuracy of the extracted trap distributions for . As obtained, the -channel LDD device exhibits a continuous build-up of traps in time. In the channel region, traps are generated in a very low density. In the LDD gate/subdiffusion region, the injection occurs from the conventional field peak, as shown in Figure 3.48. The traps are generated in the whole subdiffusion region, but in a low amount. Many more traps are produced in the LDD region near the gate edge under the LDD spacer. These traps we attribute to the injection close to the LDD field peak ([511][355]). Note that the LDD field peak is smaller than the conventional field peak, Figure 3.48. The trap distributions are quite narrow in this region (a few ). A disagreement between the experimental and calculated characteristics is found at low base levels , Figure 3.47. We are not able to extract the trap density deeply in the LDD region towards the drain and to reproduce a large increase in the charge-pumping current in the long-tail region. In this region the charge-pumping current is produced only by a weak fringing effect.

Significant current in the long tail of the stressed -channel LDD devices is observed in other measurements as well [384]. By increasing the amplitude of the gate signal the trap distributions around the peak value could be obtained with a much better accuracy and the interface can be scanned deeper in the LDD region, as explained in Section 3.5.3 and Appendix E.

The trap distributions we obtained differ qualitatively from those extracted from the gated-diode current measurements in [16][15]. In these papers, two peaks in the spatial trap distributions are found, which merge for long stress times due to the shift of the conventional field peak. In the distributions we extracted, the peak at the gate edge is much higher than the trap density near the conventional field peak. Due to a low generated trap density in the LDD subdiffusion region the shift of the conventional field peak towards the drain [499], found by the gated-diode recombination current measurements in [16], is negligible in the analyzed device, as presented in Figure 3.48. Note that we have confirmed by numerical simulation that the traps in an amount of are indeed able to shift the conventional field peak in the analyzed MOSFET. A small lowering in the LDD field peak is the only change in the field distributions in the analyzed MOSFET during the observed stressing time. That significant amount of both, electrons and holes are injected in -channel LDD devices mostly into the LDD spacer-oxide close to the gate edge, but not into the gate oxide above the subdiffusion region is also found by simulation of injection [183]. The differences between the results from different sources could be attributed to the different quality of the spacer oxides and the different level of dopant concentration in the LDD devices.

Figure 3.49 shows the calculated time evolution of the drain-current change in the LDD device assuming the extracted trap distributions from Figure 3.46. The calculated degradation can be well modeled by a power-law relationship

with a slope of . Acceptor-like interface states influence the drain current twofold (-channel devices): (1) by increasing the local resistance due to trapping of negative charge, which decreases the drain current and (2) by decreasing the local carrier mobility close to the interface due to scattering on the interface charge. The squares in Figure 3.49 are calculated by neglecting the second effect, whereas the circles depict the results when the second effect is accounted for. The slopes of both curves are very close to each other. Consequently, the second effect only shifts the degradation characteristics upwards without changing its shape (on the double-log scale). The surface scattering due to the interface charge is modeled by the relationship

In 3.134, is the surface mobility related only to the surface charge scattering. is the constant of proportionality, is the reference temperature, is the inversion-layer charge density at position and is some reference density. is combined with the surface low-field mobility by employing the Matthiessen's rule

to obtain the total surface mobility at low longitudinal fields in the channel. In 3.134, is the total density of the charged sites at the position . The proportionality has been justified both, theoretically [392][80] and experimentally [451][392][290][184] for charge uniformly distributed along the interface. A deviation from found at low [184] is irrelevant at room temperature in practice. The exponent of the temperature-dependence equals to for electrons, as derived theoretically and confirmed experimentally for room and low temperatures in [392]. The factor models the impact of the moving charge on the scattering due to the screening

effect. By increasing the scattering becomes weaker and increases. Experimental work in [290] has shown that for electrons is approximately constant at high , having a value of at and at . By fitting the experimental data in [290] we calculated for electrons assuming and . This value of is coherent with , calculated for from [451] and used in [414] (assuming and ). The attenuation of the effect of the scattering due to interface charged sites when moving from the interface towards the bulk is described empirically by function with , which is larger than the largest inversion-layer width of interest (at low fields perpendicular to the interface). Formulation 3.134 neglects the two-dimensional effects due to the variation of along the interface and accounts for the screening only through the total inversion-layer charge (no -coordinate dependence).
To be complete in our analysis, the measured changes in the drain current should be compared with the calculation in Figure 3.49. Unfortunately, these data were not available.