4.1 Interband Tunneling in ULSI MOS Devices

Interband tunneling in the gated diodes has already been investigated and modeled in mid 1960s ([211] and references cited therein). For this effect to occur, very high fields are necessary between the drain and the gate-oxide. Such large fields are common in submicrometer MOS devices with thin oxides. Interband tunneling produces several, mostly undesired, effects in MOS devices:

• It is a source of drain-junction leakage in thin-oxide MOSFETs. This current can be distinguished from other leakage processes by its weak temperature dependence (small negative temperature coefficient of the voltage at a constant current) and a strong field dependence. The later effect is manifested as a strong dependence on the oxide thickness and the drain-gate bias [213][69][59][58][57]. In addition, the current is independent of the effective channel length, so far the channel is not very short (a few tenths ). It flows from the drain towards the bulk in -channel devices. Band-to-band tunneling is the only leakage source at low temperatures () and lower lateral fields for which the impact-ionization is still negligible.
  The leakage current depends on the doping level and the profile in the junction. The effect is independent of the channel doping. For a low concentration in the junction ( drain) the band-bending is large, but the average field along the tunneling path is low because of a long tunneling distance. For high concentration , the band-bending is insufficient to enable tunneling, in spite of very high fields. Both conditions, high fields and a sufficient band-bending are fulfilled in a narrow intermediate doping range . The leakage of a single-implanted (As) drain, LATID (large-tilt-angle implanted) drain and an LDD (P-doped) structure have been compared in [213], a single-implanted (As) drain, TOPS (fully-overlapped P/As) and an LDD (P-implanted) drain in [362] and a single-implanted (As) drain, a double-diffused / (P/As) drain and an LDD in [58]. It follows that a low-doped LDD with a surface concentration less than a critical value of about yields a significant suppression of the tunneling leakage. This is consistent with the design against the conventional hot-carrier aging. However, because the series resistances of MOSFETs increase unacceptably for such low LDD concentrations a compromise in the drain engineering is necessary [57]. The LDD junctions are not applicable in EPROM cells and the BBT leakage is an important concern in design of these devices.
  Note that for tunneling occurs in both, drain-bulk and source-bulk junctions.
  Due to the work-function difference, tunneling is larger in the devices which have the gate of an opposite type with respect to the channel. E.g. the leakage current is larger in -gate/-channel than in -gate/-channel MOSFETs.
  Interband tunneling poses a limit to the minimal allowed oxide thickness. As shown by experiments, for supply voltage and a tolerable leakage of ( of device width) the minimal oxide thickness is estimated to be [57]. For the effect, only the oxide thickness in the gate/drain overlap region is interesting. The latter can be larger than the nominal oxide thickness in the channel region, due to the bird's-beak produced by the gate reoxidation.
• Interband tunneling is a source of leakage in memory cells. Regarding this type of leakage, different DRAM storage cells have been analyzed in [360][343][26]. The effect increases the charge loss from the storage node in addition to other mechanisms: trap-assisted tunneling and thermal generation. Thereby, it reduces the refresh time. This effect has been becoming a serious concern due to the very thin (SiO-equivalent) oxides applied for the storage capacitors in the high-density DRAMs (from 4Mb to 256Mb and further).
• Interband tunneling causes a hot-carrier degradation in the static bias conditions. The injection of hot majority carriers into the gate oxide (holes in -channel devices) has been found in connection with the avalanche multiplication many years ago [489][336][45]. An equivalent effect has been observed for the holes generated by interband tunneling in the gate/drain overlap region as well (-channel MOSFETs) [223][189][70]. This electrical stress is called the BBT-stress. The holes left by tunneling are initially cold. While leaving the deeply depleted region they are accelerated, at first shortly in a high field perpendicular to the interface (the attractive gate field) and further in a high lateral field due to the drain-bulk bias. Becoming hot, some of them are injected into the oxide after a redirectional collision (an isotropic phonon scattering). Note that the oxide field is hole-attractive along the whole interface. The injected holes do not only produce the negative gate current, but are also trapped in the oxide. For the effect to occur, a high bias is necessary in addition to a high bias. The trapped positive charge degrades the MOSFET characteristics (-channel devices): the threshold voltage slightly decreases and the transconductance increases [482][286][285][284][223]. The effect can be clearly seen in the stacked-gate EEPROMs, where the injected holes, due to the BBT-stress, recombine by the electrons stored in the floating gate, leading to a significant decrease in the programed threshold voltage (program disturb) [522]. In addition, the holes trapped in the oxide reduce the surface field in the tunneling critical area, thereby they suppress tunneling and the leakage current decreases. The degradation tends to cancel out itself. This effect corresponds to the known walk-out in the avalanche gated-diode breakdown [489][45]. The trapped holes can be neutralized by a subsequent short electron injection, like in the conventional electric stress [194] and the GIDL characteristics recover [286][285][284]. They even recover over the initial value for the virgin devices, indicating that a net negative charge is generated after the electron trapping. This charge is larger when the BBT-stress is performed before the electron injection. These facts suggest that the electrons are captured not only by the trapped holes and the native neutral electron traps, but also by the neutral traps generated while injecting the holes [482]. The evolution of this type of degradation at different stressing conditions is studied in [285]. It is expected that the BBT-induced degradation appears in -channel devices as well (electron injection) [223]. The studies in [387] show, however, that the leakage current in -channel MOSFETs increases after the BBT-stress, but not decreases as expected due to an electron trapping. The positive polarity of suggests that the electrons are indeed injected. It is speculated that the increase of the leakage results from trap-assisted tunneling over the acceptor-like interface states generated in the BBT-stress [387].
• This effect produces an enhanced degradation in the transient bias conditions. Let us suppose that a pulse signal is applied on the gate and a constant bias is hold on the drain of an -channel MOSFET. The pulses draw the device between the on-state and the off-state, alternatively. In the off-state, the BBT-stress occurs and the holes are injected into the gate-oxide. In the on-state, the electrons are injected into the oxide, leading to trapping of electrons on the holes and on the neutral traps generated in the BBT-stress. In the subsequent off-state, interband tunneling is enhanced by the negative net charge trapped in the oxide above the tunneling region. The hole injection increases. As a consequence, an enlarged amount of the electron neutral traps is created. Evidently, a positive feedback effect is involved at the stressing in the AC conditions [482].
• Electrical stress changes the interband-tunneling characteristics. The stress induces a damage which depends on the stressing bias and the type of the device. Moreover, the changes in the GIDL characteristics after the stress depend on the type of the damage. It is worth to point out that several experimental GIDL data presented in the literature for different stressing conditions are completely consistent with the present understanding of the hot-carrier degradation obtained by the conventional methods like the observation of , , and the charge-pumping measurements. The effect of fixed oxide charge and interface traps which are localized in the drain junction on the GIDL characteristics of an -channel transistor is shown in Figure 4.1. The characteristics are calculated by a two-dimensional numerical model presented in the following section. As expected, in -channel devices positive fixed oxide charge shifts the subthreshold curve towards more negative gate voltages and negative charge shifts the characteristics towards more positive voltages. The shift is fairly parallel, although not strongly, because it is influenced by the spatial distribution of the charge due to moving of the position of the active tunneling area with changing terminal bias. Contrary to the often believe in the literature [455][279][5][4] the interface states are not empty when the surface is depleted, but they are charged according to the non-steady-state occupancy function governed by the electron and hole emission processes

   

  If trap-assisted tunneling occurs, the occupation is influenced by this effect as well. Therefore, with respect to the pure electrostatic influence, interface states induce a shift of the GIDL characteristics like fixed charges do, even at very negative bias (-channel devices), as has been properly assumed in some studies [111]. Assuming a uniform density of traps across the forbidden band, nearly half of interface states are charged in the deep-depletion conditions. This conclusion is completely in an agreement with the calculations shown in Figure 4.1.
  The experimental results for -channel devices in [404] show a significant increase in the GIDL current after the channel hot-electron injection and the electron trapping in the oxide. The same result is reported in [279][278], where the stress at high results in a quite parallel positive shift of the GIDL characteristics. In these cases, the interface state generation was small. The stress performed at has resulted in an increase of the GIDL current and a non-parallel shift of the characteristics [279][278][111]. It is known that the stress at results in a maximal generation of interface states and a small amount of holes trapped in the oxide for -channel MOSFETs. Accounting solely for the electrostatic effect, the interface states of acceptor-type induce a positive shift and slightly decrease the slope of the GIDL characteristics, as is obtained in Figure 4.1. They are, probably, not able to decrease the slope so much as the measurements show. In order to explain the non-constant increase of the GIDL current, interface-state-assisted tunneling has been suggested in the literature. In -channel MOSFETs the electrons trapped in interface states which are located in the lower half of the band gap tunnel towards the bulk, leaving the traps unoccupied. The traps which become empty are filled by the hole emission. In -channel devices, the valence band electrons tunnel towards the interface into empty interface states which are suited in the upper half of the forbidden band. The trapped electrons are emitted into the conduction band. A correlation of the increase in the GIDL in the low-field region and the interface state density is found for both, -channel and -channel MOSFETs in [67], where the interface states are created by the Fowler-Nordheim stress. After annealing at C the interface states vanish and the GIDL characteristics recover very closely to that of the virgin devices. Such effect of an anneal is reported in [111] as well. The increase of the leakage is much stronger in -channel than in -channel devices [67]. An unexpected increase in the GIDL in -channel devices is found in [387]. It is attributed to interface-trap-assisted tunneling and the acceptor nature of the interface states. A correlation between an increased BBT leakage and the interface state density is reported for -channel transistors in [134] as well, where the interface states where produced by the oxide nitridation and removed by the reoxidation. The stressing of -channel transistors carried out in [111] at different gate voltages (for the , and in the subthreshold region) has yielded a negative shift of the GIDL curves due to an electron trapping and an increase of the GIDL in the low-field region. The later has also been explained by interface-state-assisted tunneling.
  An -ray irradiation is shown to shift parallel the GIDL characteristics of -channel MOSFETs towards the more negative due to positive charge induced in the oxide [5]. The shift of the characteristics of -channel transistors is positive and non-parallel. It is attributed to the combination of the positive shift on the voltage axis due to the positive charge induced in the oxide and an eventual positive charge in the donor-like interface traps (at low gate biases) and due to an increase in leakage caused by interface-trap-assisted tunneling [5]. For both device types, a subsequent anneal at C has been resulted in a complete recovery of the GIDL characteristics towards those of the virgin devices.
  Note finally that the trap-assisted nature of the increased GIDL in the low-field region can be confirmed by measuring the GIDL characteristics at different temperatures. Such systematic investigations has not been carried out yet.

Among the negative consequences of band-to-band tunneling, one can also benefit from this effect:

• The nonvolatile programing memories with a high injection efficiency could be designed. By applying a reverse back-bias the surface can be drawn into deep-depletion, resulting in a large surface band-bending. Different methods to induce the deep-depletion are proposed in [353][65]. If the dopant concentration is high close to the interface, the tunneling path is short enough to enable significant tunneling of electrons towards the interface (devices with -type bulk). The generated electrons are collected by the source and/or the drain. The holes left close to the interface are accelerated towards the bulk in a very high field which holds inside the deep-depletion region. Gaining a sufficient energy, they produce the electron-hole pairs by the impact ionization. The electrons generated by the avalanche effect deeply in the bulk move towards the interface, being accelerated by the attractive field in the deeply-depleted region. Some of them escape collisions, are not redirected and gain sufficient energy to be injected into the oxide. It has been experimentally confirmed that this, so-called band-to-band induced substrate hot-electron (BBISHE), injection has a very high injection efficiency . It ranges from to [68][66][65], which is much larger than those common in the channel hot-electron injection (). Comparing with the second programing mechanism, i.e. Fowler-Nordheim tunneling [270][135], the BBISHE occurs at much lower oxide fields () for the same current density, enabling an order of magnitude larger electron fluency through the oxide before the oxide failure. As a consequence, the memories applying this programing mechanism should have an enlarged endurance compared with the present non-volatile memory cells.
• An active MOS device whose operation is based directly on band-to-band tunneling has been proposed almost three decade ago [211]. Recently, parallel with studying the undesired leakage current caused by band-to-band tunneling, it has also been proposed to utilize this effect for the device operation [460][25]. All proposed devices consist of a heavily doped gated-diode. Heavily doped areas of the opposite types (source and drain) are separated by a moderately doped bulk, which ensures high breakdown voltages of the structures. This low-doped area is deeply depleted under the gate in regular operating conditions. Tunneling occurs in the heavily doped region of the same type as the bulk. The gate is the control electrode. The generated electrons are collected by the region. The holes flow either into the bulk [25] or drain [460], which depends on the place where the second electrode is connected. Note that the devices with bulk have been realized as well. Such ``quantum'' devices do not exhibit classical short-channel effects (like the threshold voltage roll-off) and the conventional hot-carrier degradation. They suffer, however, from the new hot-carrier effect mentioned above. A transconductance which monotonically increases with and a very high output conductance of these transistors are demonstrated [25]. The devices exhibit a nice output characteristics, i.e. with as a parameter. These devices are highly scalable down to the range, but they have slab driving capabilities due to very low operating currents in the /( gate width) range. Therefore, they are interesting for some future low-power high density IL-like circuits. Among the single-crystal silicon transistors, this type of devices has been realized in the polycrystalline thin-film as well [318].
• Interband tunneling can be exploited as a monitor for hot-carrier degradation of MOSFETs. As noted above, the GIDL characteristics change after the hot-carrier stress. Assuming that only oxide trapped charge is generated, the GIDL characteristics are shifted on the voltage axis in approximately parallel manner. This shift enables one to measure the amount of fixed oxide charge [455][399][278][4]. The technique is applicable for both, positive and negative trapped charge . Note that the measured gate-bias shift refers to fixed oxide charge in a narrow interface area where interband tunneling occurs. This interval does not necessary correspond to the most damaged region. Moreover, it slightly moves along the interface with terminal voltages. As a consequence, the shift of the GIDL curves is not parallel in the general case. Using this technique a logarithmic time-dependence of the build-up of trapped charge is found in [455][399], which is in accord with the charge-pumping measurements [30]. There is an opinion in several works, that the GIDL characteristics of the reversely biased drain junctions are only influenced by fixed oxide charge, whereas the acceptor-like interface states do not influence the GIDL characteristics [455][279][5][4]. As we already explained, the traps are not empty in the deep depletion, but are partially charged positively or negatively, according to their nature. Therefore, they contribute to the measured shift in the GIDL characteristics in addition to oxide trapped charge, even at very negative (-channel MOSFETs). Although the shift caused by interface states is not parallel, it can be used to estimate the density of the net charged interface states, as has been done in [111]. Moreover, interface-state-assisted tunneling can take place in the reversely biased junctions as well. In my opinion, the GIDL data must always be supplied with additional interface state density data (measured by e.g. charge pumping), in order to extract information on the damaged region from these data. Regarding the forward biased gated diode, the current increases when the interface states are generated in stress, probably due to trap-assisted tunneling. Since the forward tunneling current depends on both, fixed oxide charge density and interface state density [4], only a qualitative information on these quantities is available.