1 Introduction

In 1959, Atalla et al. have demonstrated a passivation of silicon surface when an oxide-layer is grown on silicon [17]. The way to propose a useful Field-Effect Transistor (FET) was open; in 1960 Kahng and Atalla have discussed a silicon Metal-Oxide-Semiconductor (MOS) transistor with SiO oxide [234] and Hofstein and Heiman have proposed a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in 1963 [209]. An extensive theory of MOSFET operation has been developed in next few years by Ihantola et al. [224], Sah, Reddi and Pao [391][390][382], Hofstein and Warfield [210] and several other researchers. Since that time, a huge amount of research in the MOS technology, devices and circuits has been resulting in a dramatical reduction in size and improvement of the MOSFET performance. As an interesting fact, the basic MOSFET structure and the principle of the operation, however, did not change. Most of the research effort has been put into solving many problems which have occurred either as a consequence of size reduction or because of the application of new technology processes. Today, MOS devices of the Very-Large-Scale-Integration (VLSI) level, which are common in industrial production, have the gate length of and the gate-oxide thickness of . The development of CMOS technologies in the range from down to is the topic of the current activities, e.g. [351][301][93]. Such systems can contain several million transistors on a single chip; we may call them the systems of Ultra-Large-Scale-Integration (ULSI). The research at the level of - and - has already been started for both, -channel and -channel MOSFETs several years ago, e.g. [473][472][394][393]. Moreover, MOS devices with the channel length as small as - have been demonstrated [186][185]. For the later devices, the channel length equals to only several tenths interatomic distances in silicon crystal. They show strong tunneling effects. Nevertheless, it is expected that the gate length of is the limit for the CMOS technology, regarding the performances of the logical gates, stray capacitances, delay in the interconnection lines and the economical aspect.

The reduction in device size causes several problems in MOS transistor design. They may be roughly divided into several groups:

• The problems due to an increased electric field strength:
  • the oxide reliability; Time-dependent dielectric breakdown (TDDB) is strongly dependent on the oxide thickness, supply voltage and the technology process (the density distribution and the size of defects).
  • the reliability problems caused by the hot-carrier effects in silicon: the avalanche multiplication, the avalanche breakdown and the hot-carrier injection into the oxide. Some of these effects are discussed in more detail in this work.
  • the mobility reduction due to the high field perpendicular to the interface and the high field parallel to the interface; The transit time increases and the drain current decreases, causing that the driving capabilities of the devices and the speed of the circuits degrade.
  • the reliability problems and the leakage current caused by the tunneling through the gate oxide
• An increased dissipation.
• Increasing resistances of the contacts and the interconnection lines.
• The electromigration in the contacts and the interconnection lines. The contacts and interconnectors must be low resistance and high reliable. For the electromigration, the mean time til failure obeys a law , where at low and at high current densities .
• The errors caused by ionized irradiation. With shrinking dimensions the total charge in devices reduces with a square law. Under some critical charge the error probability due to ionized irradiation increases rapidly. The ionization can be produced by the -particles from the chip-package or by the cosmic rays.
• The problems related to the distributions of potential and charge:
  • the drain-induced-barrier-lowering (DIBL) effect; The turn-off characteristics degrade.
  • the threshold voltage reduction due to the charge-sharing effect
  • the punch-through effect
  • the parasitic bipolar-transistor action (between source, bulk and drain); With reducing effective channel length this breakdown voltage (BVCEO) reduces because the diffuse length of the minority carriers does not scale down.
  • threshold voltage variations; sensitivity to the process parameters and the fluctuations in the dopant distribution
  • series resistances; There is a strong demand for the low-resistance shallow junctions.
  • the polysilicon-gate depletion effect
• Statistical variations increase with reduction of dimensions; We have to take care of the spatial tolerances and the variations in the dopant concentration.

In the early work on MOSFET modeling in 1960s, the analytical methods have been commonly applied [84]. The analytical MOSFET models are very accurate assuming that the two-dimensional effects are negligible (long channel devices) and that the bulk is uniformly doped. The analytical models can even account for the complex field-dependent mobility relationships within the classical drift-diffusion transport approach [164]. To overcome the shortcomings of the analytical models due to the two-dimensional effects, the researchers and engineers have started to investigate and apply the pure numerical approaches to MOS device modeling in the late 1970s. This field has been growing parallel with the rapid improvements of the computer performances in 1980s and 1990s. Considering the realistic MOS devices, the analytical models can only yield approximate solutions, but they enable a good inside into the physics of the problem. By using the numerical methods, the exact solution can be easily achieved for the assumed models of the physical parameters. However, the physical inside into the problem can be lost; very often in the engineering practice the numerical simulation reduces to obtaining the result in the form of numbers or to fit the experimental data. In spite of very good agreement between the numerical calculations and the experimental results, the extracted parameters of the employed physical models are very often questionable. This is mostly caused by inadequate physical models, neglecting some important physical effects, improper parameter extraction or the (discretization) error in numerical calculations. We believe that only a close interplay between the analytical and the numerical approach is able to provide an improved modeling of small MOS devices. Some methodologies should always be applied: (1) The discretization error in the numerical models can be evaluated by comparison with the analytical results for the cases where the exact analytical solution exists. (2) As opposed, the quality of the approximative analytical models (the error and limitations) can be investigated by employing the numerical simulations to obtain the referential results with a high accuracy. (3) The simulation results must always be understand in complete. Such an approach can provide a better inside into the physical effects in devices, similarly as the analysis of the experimental results can do. These three research methods have been extensively employed in this work.

Most modeling studies of small MOSFETs deal with the hot-carrier transport. In this work, we have considered other topics which have attracted a bit less attention in the literature. The first problem is the voltage drop in the gate area, which is caused by the penetration of the high electric field into the nondegenerately doped gate. As a consequence, the gate area becomes non-equipotential, which must be taken into account in accurate MOSFET modeling. This effect results in a reduction of the effective gate bias, causing a degradation of the device performance. It alters the device static characteristics and the capacitance characteristics as well. This effect must be accounted for in the measurements and analysis where the oxide field, particularly at the gate corner, is important. The effect depends on the square of the oxide thickness, which posses additional requirements on the gate engineering for the thin-oxide ULSI devices. A significant part of the work considers the charge-pumping effect in MOS devices. This effect is interesting from two aspects: for the measurements of the amount and the spatial and energy distributions of the interface and bulk traps and for the application in the operation of some devices. The charge-pumping measurements are direct; if no traps are present in device, the signal only consists of small parasitic component. Note that most of the known techniques to measure the trap properties are indirect. In addition, the charge-pumping measurements are fast, accurate, reliable, simple and do not require complex and expensive equipments. Since the early 1980s, the charge-pumping effect has been extensively investigating. Several analytical models have been developed. They are commonly used to extract the trap parameters from the experimental data. The analysis of the charge-pumping phenomenon in MOSFETs is an essentially two-dimensional transient problem. Thereby, it cannot be solved by analytical means in general. In this work, we have developed a numerical transient two-dimensional model of MOS devices including selfconsistently for the trap dynamics. This model has been extensively applied to study the charge-pumping effect. For the first time, we have evaluated the accuracy of the present analytical models, their limitations, the applicability of different measurement techniques and have studied the parasitic effects involved at the experiments. It has been found that the physical explanations and the models given in the literature are too simple in several cases; systematic errors have been found in the present approaches. In addition, improved analytical models of the charge-pumping effect are derived. One of the most important application of the charge-pumping effect is to analyse the MOSFET degradation. By using the rigorous numerical approach we have studied the degradation by means of the model-experiments. An unexpected effect is found in this study, that the surface charge localized in a finite width induces in some cases a much smaller shift in the charge-pumping characteristics than the shift calculated for the uniform charge. This effect has been analysed in more detail and a general analytical theory has been derived. We note that the rigorous transient modeling of MOS devices including the trap dynamics is also important to analyze the SOI devices, to model the Deep-Level-Transient-Spectroscopy (DLTS) signals for MOS devices and to study the Random-Telegraph-Signals (RTS) and, particularly, very large amplitudes of RTS observed in small MOSFETs which can even be a source of failure in the circuits [350]. Much further work is necessary in these fields. As the third topic we have analyzed the interband tunneling in the drain-bulk and source-bulk gated-diodes in MOSFETs. The tunneling effects in the heavily doped gated-diode have been reported a long time ago, e.g. [211]. In the late 1980s, this effects has attracted more attention due to the application of very thin oxides in the high-density memory cells and small MOSFETs. The interband tunneling is not only an undesired effect which can increase the subthreshold leakage significantly, but can also be employed for the device operation and as a monitor for the hot-carrier degradation of MOSFETs. In spite of several works published on this topic, it should be noted that the state of the art in the physics and modeling of the interband and the interface-trap-assisted tunneling in silicon MOS devices is still unsatisfying.