1.3 Electrical and Physical Properties

With the same speed as integration density of semiconductor devices increases, the requirements of material properties have to be adjusted accordingly which also implies improvements of fabrication technology in terms of purity of the material sources as well as the uniform applications on reactor-scale. Hence, the fluctuation of the electrical and thermal conductivity and of the permittivity has been dramatically reduced to obtain devices with uniform characteristics and with improved reliability. Many enhancements have been proposed by former editions of the ITRS [10] and most of them have been achieved in advance. Only a few forecasted technologies are missing. Most of the missing parts are related to too high power densities or too high current densities [3]. This lack of achievements leads to more research activities and the rapid development of new types of devices and has pushed the effort to find alternative materials for device interconnect structures [19,20], dielectrics [21,22], and for the semiconductor device parts of microelectronic devices [15,23].

Figure 1.2: Transmission electron microscopy (TEM) picture of a typical $35$ nm MOS transistor [15] (a) and a typical gate dielectric layer structures [16] (b) with a thickness of $1.5$ nm.

To overcome these types of problems, the current technique is to use other materials which have a better performance than $\mathrm{SiO_2}$ . The requirements for alternatives are to provide a higher dielectric constant, under the constraint that the life-time and the leakage current meet the specifications of the design.

By the introduction of materials with smaller lattice constants, the number of atomic layers slightly increases, but the possible enhancement is less than approximately 20% due to their similar lattice constants compared to that of $\mathrm{SiO_2}$  [24,25]. To achieve better results for down-scaling, it is necessary to introduce materials which perform better at large thicknesses than $\mathrm{SiO_2}$ but behave similar to $\mathrm{SiO_2}$ in terms of insulation and interface behavior. To choose the appropriate materials for a proper operation of a FET, the value of the control capacitance between the gate and the channel must not fall under a certain threshold value for the capacitance.

The control gate capacitance $C_{\mathrm{GB}}$ can be roughly estimated by using the formula of a capacitor for parallel plates

$$C_{\mathrm{GB}} = {{\varepsilon_0}}{{\varepsilon_{\mathrm{r}}}}\frac{A}{d},$$ (1.1)

where ${\varepsilon_0}$ is the dielectric constant for the matter-free space, ${\varepsilon_{\mathrm{r}}}$ the material-specific dielectric constant, $A$ the effective area of the gate electrode, and $d$ the average distance between the gate contact and the channel of the FET. For real devices, the capacitance of the control device is a function of the work function of the gate contact material, the channel doping, and the applied voltage as presented in Figure 1.3.

Figure 1.3: Capacitance-voltage characteristic of a typical MOS transitor with a gate dielectric thickness of 1.2nm.

However, to improve the prediction of the electrical behavior of state-of-the-art devices the range of validity has to be considered in advance. For this particular example of a MOS capacitance, a more accurate approach is required to obtain rigorous models for the depletion zones in the gate material for ${\mathrm{polySi}}$ and the voltage dependence of the MOS capacitance structure.

In order to increase the value of the gate capacitance, the area $A$ and the dielectric constant ${\varepsilon_{\mathrm{r}}}$ have to be increased or the distance of the gate dielectric layer has to be decreased. Due to technology and cost-efficient reasons, the area has to be kept constant. The thickness of the gate dielectric layer cannot be reduced any more due to the hard limit of the lattice constants. The only remaining variable part in (1.1) is the material-specific relative dielectric constant ${\varepsilon_{\mathrm{r}}}$ . If there exist materials which behave like $\mathrm{SiO_2}$ but have a higher ${\varepsilon_{\mathrm{r}}}$ , the thickness of the gate dielectric can be increased while the overall gate capacitance remains constant or increases.

By using materials with lower dielectric constants than $\mathrm{SiO_2}$ the capacitance from (1.1) can be reduced as well. This can be applied for dielectric layers in between of interconnect lines to reduce for instance the cross-talk of these lines due to the reduced dielectrics which are currently widely used in VLSI devices.

Another considerable performance improvement for VLSI devices was the replacement of Al by Cu for the reduction of the specific line resistivity for high speed applications. This material change has brought many improvements, e.g. less power consumption due to the reduced resistivity of the interconnect lines, but also a lot of new challenges for the device fabrication processes. Hence, due to the higher diffusivity of ${\mathrm{Cu}}$ , new barrier layers had to be introduced [26]. Moreover, for special applications, where the performance of Si-based materials is not sufficiently enough, new materials have been investigated in order to improve the overall performance and in addition also the reliability of these devices.

Some these special applications are memory cells, which require high dielectric constants in order to provide capacitances at very high package densities, so $\mathrm{SiO_2}$ has been partially replaced by Ta compounds [27] or by Perovskite materials^1.2 [29] for capacitor materials.

All these measures require a considerable effort in terms of development, time, and money. Hence, the industrial manufactures try to exploit the available technology node as long as possible to save money. This sometimes leads to quite unconventional, but very effective results in device designs [30], to new improvements in process technology [31] and material science [32].

The use of alternative materials has posed new challenges, which have to be identified and considered as well. For instance, the substitution of Al by Cu has increased the conductivity and decreased bulk electromigration and therefore the long-life reliability, but due to technology reasons, parasitic side effects occur at the Cu interfaces [33]. First, Cu easily diffuses into ${\mathrm{Si}}$ and $\mathrm{SiO_2}$  [34,35,26]. Therefore, a new barrier layer has to be introduced into the device structure. Moreover, the adhesion between ${\mathrm{Cu}}$ and the barrier layer is quite weak, which causes a high disorder of the crystal lattice structure at the side walls of the metal lines. Hence, high-speed diffusion paths have been established and the desired enhancement of the long-life reliability is not as high as estimated at the introduction of this technology [36].