Emulation and Simulation of
Microelectronic Fabrication Processes
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1.2 Motivation and Research Goals
All the discussed processing steps must be configured to tie perfectly into the entire process flow in order to yield robust device performances. Since carrying out physical fabrication is very expensive, especially at advanced nodes,
the simulation of these process steps can help to understand common problems encountered in the fabrication and thus can strongly decrease the cost of optimising manufacture and designing new devices. It can also assist in tuning
the fabrication settings and providing an insight into fabrication-induced variability and reliability.
This work builds on simulation efforts conducted previously at the Institute for Microelectronics, TU Wien, based mainly on the topography simulator ViennaTS [20], which employs the level set (LS) method to describe material
interfaces. However, due to design restrictions, this simulator does not allow for the description of volume properties of materials, which is crucial for the modelling of certain fabrication processes. Furthermore, the LS method does
not allow for the efficient emulation of fabrication processes. This means, that a process must be modelled in time and material interfaces moved discretely. However, for certain processes it is much more efficient to simply describe
their geometric effect on a structure, which is referred to as emulation [21]. Additionally, due to the software design of ViennaTS, it cannot be combined with other simulators straight-forwardly to create a full DTCO toolchain.
Therefore, the goal of this work is to create a broadly applicable high performance simulation framework for the modelling of semiconductor manufacturing processes. This includes fast structure generation using emulation methods,
as well as highly sophisticated physical simulations. This framework will allow for the fast creation of masks and initial geometries for microelectronic fabrication processes. The development of new fundamental methods are
required to perform process emulation directly on a level set, which is one of the main goals of this work.
Additionally, a modelling framework for highly physical process descriptions, including transport, surface and volume reactions, as well as their effect on material interfaces will be implemented. This requires the application of
stochastic methods, such as ray tracing, to model the transport of chemical reactants above the wafer. This allows for the straight-forward development of physical models with great flexibility regarding the computational methods
required for the description of physical phenomena. This framework is then used to develop and apply sophisticated physical models, as well as efficient emulation models, describing the etching and deposition of materials during
the manufacture of semiconductor processors.
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