Emulation and Simulation of
Microelectronic Fabrication Processes
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1.3 Outline of the Thesis
The fundamental mathematical concepts and numerical methods required for the modelling of semiconductor fabrication simulations are presented in Chapter 2. These include
numerical material and interface representations, as well as the description of material evolution in time. Common modelling approaches and their mathematical foundation are presented, highlighting their relative benefits and
limitations. A comprehensive review of the LS method and different variants thereof is presented, as well as commonly applied discretisation schemes for space and time.
The fundamental concepts for modelling particle transport in chemical reactors are introduced in Chapter 3, focussing on the specific requirements for semiconductor
manufacturing and the related processing equipment used in this field.
In Chapter 4 the implementation of the numerical concepts introduced in Chapter 2 and Chapter 3 within the software toolchain developed in the course of this work is presented in detail. The applied algorithms and implementation details thereof are provided, highlighting
potential pitfalls and limitations of the underlying methods when applied to the simulation of semiconductor fabrication processes. Results generated by individual components of the software toolchain are presented to guide the
reader visually and show the capabilities of the presented simulation framework.
Chapter 5 includes a collection of complete process models, discussing their physical and chemical foundation and input parameters. Starting with models for CVD, selective epitaxial growth
(SEG) and several wet and plasma etching processes, more complex fabrication steps, such as the Bosch process, are presented. Each model is discussed in detail, including physical mechanisms dominating the process, as well as the
required input parameters and results for typical structures. Furthermore, the fundamental difference between process emulation and process simulation models is presented using the resulting geometries of the respective process
models. A number of process flows for entire devices and circuits are presented thereafter. These include the fabrication of a replacement metal gate (RMG) FinFET at the 22 nm technology node, as it is currently
produced in many industrial applications, and a stacked nanowire transistor which is a commonly proposed solution for transistor scaling beyond the 5 nm technology node.
Finally, Chapter 6 provides a summary of the findings of this work, concluding with an outlook for future directions of research.
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