1.2  Scope of the Thesis

Recently, it has been shown that a fundamental Boolean logic operation called material implication (IMP) is naturally realized using TiO memristive switches to enable stateful logic by using memristive devices simultaneously as latches and logic gates [75]. Stateful logic inherently provides a non-volatile logic-in-memory architecture with zero-standby power and is free from the leakage power issue. It also allows to shorten the interconnection delay by eliminating the need for intermediate sense amplifiers as well as the data transfer between separate memory and logic units and, by that, to lift a prerequisite of the Von Neumann computing architecture. In this thesis, implication logic gates are studied and optimized using an accurate nonlinear memristive device switching model. It is shown that due to error accumulation in TiO memristive devices, spintronic devices are preferable to build up stateful logic circuits, as they do not show error accumulation and exhibit almost unlimited endurance.

A novel spintronic stateful logic gate is proposed, which stores the result of the implication logic operation directly into the memory devices. This thesis covers several issues regarding device, circuit, and architecture levels of the proposed logic framework. Special emphasis is put on the performance analyses of stateful logic devices and circuits and it is shown that the reliability is an essential prerequisite of stateful logic systems. Furthermore, it is demonstrated that the presented logic gate, which enables an implication logic framework, significantly improves the reliability compared to similar circuits available from literature, which are based on reprogrammable architectures to realize conventional Boolean logic operations including AND, OR, NAND, and NOR operations.

Due to an easy integration of MTJs on top of a CMOS circuit plane, hybrid CMOS/MTJ circuits are used to facilitate the generalization of the proposed logic gates to large-scale non-volatile logic circuits. An innovative idea to utilize the access transistors of the one-transistor/one-MTJ (1T/1MTJ) cells not only as on-off switches but also as voltage-controlled resistors, is presented to address an asymmetry issue in the implication logic gates and to extend the functionality of the STT-MRAM architectures to perform logic operations with no extra hardware added. It is shown that the STT-MRAM-based logic provides non-volatile logic fan-out and exhibits high flexibility with regard to the delocalized computations execution, and eliminates the need for intermediate circuitry. It also enables parallel non-volatile computations and, therefore, it is suited for implementing complex logic functions. Advantages of the MRAM-based stateful logic are demonstrated by considering the STT-MRAM-based implication of the fundamental arithmetic functions. Through design examples like a stateful full adder, the possible tradeoffs to optimize the execution time, the energy consumption, and the reliability of the MRAM-based stateful logic architectures are also investigated.

The last part of the thesis describes novel charge- and flux-based sensing schemes utilizing the unique property of memristors to memorize the historic profile of the applied current/voltage. The device history can be revealed instantaneously by measuring its varying resistance (memristance). The proposed method, which is independent of the memristor material, can be used for capacitance, inductance, and power measurements. Although inductance and capacitance sensing are far from being new problems, the use of a memristor reduces the measurement to a straightforward resistance measurement. Depending on the sensing application, particular characteristics of the memristor are exploited. In order to have the possibility of both charge- and flux-based sensing, we suggest spintronic memristors which exhibit rich geometry dependent behavior with regard to the dynamic properties of a propagating magnetic domain wall in a magnetic device. The memristive sensing method is also suited for measuring time-varying inductances and capacitances and has the potential to be used in novel inductive and capacitive sensors.