2.7 Sort and Final Test

IC manufacturing processes tend to produce significant numbers of defective parts. Without appropriate test procedures in place, the defective parts would find their way to customers and evidence themselves as poor quality. Furthermore, many ICs are used in security related systems (e.g. in a car) where it is definitely not acceptable, that only one defective part finds it's way into a system.
There are two instances of IC testing in a semiconductor manufacturing company. First there is sort which tests the IC on wafer level using probe cards similar to the procedure used at electrical test described in Section 2.6. The measurement equipment is about identical as described there, however, the architecture of the probe card is normally much more complicated, and the system is performing not only parametric but also digital pattern tests on the IC's. The metric commonly used to represent the quality of IC components is defect level (DL), also referred to as reject ratio. This is expressed by the ratio:

$$DL = \frac{N_{passed,bad}}{N_{passed}}$$ (2.15)

with $N_{passed,bad}$ as the number of bad parts which test as good and $N_{passed}$ as the total number of parts passing the test. The defect level is typically expressed in ppm. (or defective parts per million, dpm).
Figure 2.16 indicates various aspects involved in test.

Figure 2.16: The test process

During the design phase, design for test (DFT) rules [64] and [65] are enforced and checked to ensure that tests of sufficiently high quality can be generated and applied. Figure 2.17 illustrates the flow of a typical chip test, in which there are three distinct phases.

Figure 2.17: The three phases of IC testing

Each phase rejects parts, and the quantity which the chip tests reject gives rise to the defect level discussed above.