Degradation of Electrical Parameters of Power Semiconductor Devices – Process Influences and Modeling

6.2 Charge pumping for SiC-SiO2 interface characterization

The interpretation of Charge pumping (CP) experiments, as described in more detail in the review Section 1.2.2, follows a standard model [Gro+84] which is based on SRH theory [SR52; Hal52] on Si based MOSFETs. In the following, it is shown that this model is also capable to accurately describe CP results on SiC-nMOSFETs.

It is remarked that the following measurement results are displayed in terms of charges pumped per cycle [Gro+84; Aic+10c; Rya+11]

$(6.6) \begin{equation} \gls {Ncp} = \gls {Dit}\gls {dEcp} = \frac {\gls {Icp}}{\gls {q}\gls {f}\gls {A}}. \end{equation}$

This has the advantage that the area and frequency dependencies of the CP current are inherently considered to simplify comparisons. Naturally, an analysis of the density of interface traps (math image) in 1/(cm² eV) would be even more desirable. However, for a determination of the active CP energy region

$(6.7) \begin{equation} \gls {dEcp} = 2 \gls {kB}\gls {T} \ln \left ( \gls {vth}\gls {ni} \sqrt {\sigma _\tn {n}\sigma _\tn {p}} \frac {|\gls {Vfb}-\gls {Vth}|}{\Delta \gls {Vg}} \sqrt {\gls {tf}\gls {tr}} \right ), \label {eq:CPdEcp2} \end{equation}$

the material dependent capture cross section (math image) of SiC-SiO2 interface traps, the thermal drift velocity and the intrinsic carrier density of 4H-SiC are needed. Unfortunately, those parameters are only poorly determined for 4H-SiC and are therefore afflicted by large uncertainties. In detail:

• Different studies [Oui+94; Pip+05; Rud+05; Che+08; Roz08] have obtained values for the electron capture cross section of interface traps at the 4H-SiC-SiO2 interface in the range from 10⁻²¹ cm² to 10⁻¹⁶ cm². Even values as low as 10⁻⁵ cm² to 10⁻⁴ cm² [KTL96] were reported. Another study has suggested that the capture cross section depends on the energetic trap position for six layer hexagonal SiC (6H-SiC)-SiO2 MOS capacitors [Oui+94] and a similar situation is expected for 4H-SiC based MOSFETs.
• The thermal drift velocity of the carriers is reported to be around 10⁷ cm/s. Simulation results report 1.6 × 10⁷ cm/s whereas experimental results are 0.8 × 10⁷ cm/s [Vas+00]. A temperature dependent model is

$(6.8) \begin{equation} v_{\tn {th}} = v_{\tn {th},0} \times \sqrt {T}, \end{equation}$

with $v_{\tn {th},0,n} = \SI {6.74e5}{\centi \meter \second ^{-1}\kelvin ^{-1/2}}$ and $v_{\tn {th},0,p} = \SI {1.55e5}{\centi \meter \second ^{-1}\kelvin ^{-1/2}}$ for electrons and holes, respectively [Cio05].
• The intrinsic carrier density is calculated as

$(6.9) \begin{equation} \gls {ni} = \SI {1.7e16}{\kelvin ^{-3/2}\centi \meter ^{-3}} \times T^{3/2} \exp \left ( -\frac {\num {2.08e4}}{T} \right ), \end{equation}$

which is a simplification of the temperature dependence resulting from [Aya04]

$(6.10) \begin{equation} \gls {ni} = \sqrt {N_\tn {C}(T) N_\tn {V}(T)} \exp \left (-\frac {\gls {Eg}(T)}{2\gls {kB}\gls {T}}\right ). \end{equation}$

This approach gives a carrier density of $\gls {ni}=\SI {4e-11}{\per \cubic \centi \meter }$ at 25 °C. Still, other references [FBS96] report a value of $\gls {ni}=\SI {e-8}{\per \cubic \centi \meter }$ for room temperature.

The large uncertainty of these material parameters make the calculation of the density of interface traps for SiC-MOSFETs uncertain. However, a possible approach is to calculate the impact of the maximum error on the (math image) [Pob+14]. The error in becomes as small as 0.1 eV by suggesting ranges of possible values as $\gls {sigma}=\SI {e-18}{\centi \meter \squared }$ … $\SI {e-16}{\centi \meter \squared }$ , $\gls {vth} = \SI {0.75e7}{\centi \meter \per \second }$ … $\SI {2e7}{\centi \meter \per \second }$ , and $\gls {ni} = \SI {0.5e-8}{\per \cubic \centi \meter }$ … $\SI {1e-8}{\per \cubic \centi \meter }$ .

Still the number of charges pumped per cycle (math image) is primarily used to separate the influence of the particular choice of material parameters from variations in the number of interface traps.

It is remarked that in SiC MOS structures an inversion of the interface is in principle only possible at very high temperatures above a few hundred degree Celsius or if an external source provides minority carriers. For SiC-nMOSFETs the presence of the n $^{++}$ doped source/drain junctions close to the active device interface allows the inversion of the interface due to the lateral supply of minority carriers. So for MOSFETs all interface traps within the band gap can exchange their charge frequently, also during the CP measurement. In contrast, SiC MOS capacitors posses a region around the mid of the band gap with traps which are charged only once with the first use of the device [FBS96].

6.2.1 Characteristics

To check the behavior of the measured CP current, the impact of the gate area on (math image) is inspected. Fig. 6.14 displays the results of constant base level CP measurements on devices with different gate lengths.

The number of charges pumped per cycle is depicted, so the result of Fig. 6.14 is that the CP current does scale with the device area.

In Fig. 6.15 a constant base level measurement is compared to a constant peak level CP measurement.

The constant base level CP measurement shows the CP threshold voltage, defined at the gate voltage where the maximum increase of the (math image) versus is given [AN08; Aic07]. The equivalent is true for the CP flat-band voltage of the constant peak level measurement. The temperature dependence of the in this way extracted CP and values is shown later in Fig. 6.19.

Next, as shown in Fig. 6.16, the frequency dependence of the CP current is inspected.

Two different rising and falling slopes are shown to reveal either insufficient base or peak times or measurement errors due to the finite current resolution limit of about 10 pA. The number of charges pumped per cycle (math image) is supposed to stay fairly constant over a few decades of frequency. This indicates that mainly the transition from accumulation to inversion and vice versa is responsible for the measured CP current, as expected for fast interface traps [Gro+84; Aic07]. However, there exists a small but evident increase of (math image) with decreasing frequency which is usually attributed to border traps which charge during the peak time of the pulse and discharge during the base time (and vice versa) [Fle92; Pau+92; PW94]. Still, their number is roughly one decade smaller ( $\approx \SI {e11}{\per \centi \meter \squared }$ ) than the number of interface traps ( $\approx \SI {e12}{\per \centi \meter \squared }$ ).

Furthermore, it can also be seen that decreasing the rising and falling slopes increases (math image) , consistent with the standard model for CP (1.4) [Gro+84] which states that smaller rise/fall times increase the accessible energy range within the band gap . This is investigated in more detail in Fig. 6.17.

There, (math image) is fairly independent of the transition time from accumulation to inversion (rise time). In contrast, a large dependence on the fall time is seen (going from inversion to accumulation). In detail: During the peak voltage period an interface trap has captured an electron which originated from the source or the drain. During the peak phase the interface trap may re-emit its electron to the conduction band if the trap is close to the conduction band edge. If the negative charge is kept in the interface trap, two possible processes may occur during the transition from inversion to accumulation: First, the electron is emitted towards the conduction band where it returns to source or drain. Or, secondly, it is emitted towards the valence band where it is gathered by the bulk contact and contributes to (math image) . The latter process is initiated by the change of the gate voltage because of the dependence of the hole capture process on the Fermi level as

$(6.11) \begin{equation} \gls {tau}_\tn {cp} = \frac {1}{ \gls {vth}[\hspace {-0.7pt}_{,p}] \gls {sigma}_p \gls {ni}} \exp \left (\frac {\gls {Ef}-\gls {Ev}}{\gls {kB}\gls {T}}\right ). \end{equation}$

That is to say, the faster the Fermi level is changed towards the valence band edge (smaller falling time), the sooner holes from the valence band can be captured. So if a large density of interface traps is present in the upper half of the band-gap, a strong dependence on the fall time is observed. Consequently, this measurement suggests a larger interface trap density close to the conduction band edge, which is in accordance with results from CV measurements [SMA00].

6.2.2 Temperature dependence

In Fig. 6.18 the impact of the temperature on (math image) in a constant base level CP measurement is shown.

Consistent with the standard model for CP [Gro+84] and the results on Si based MOSFETs [ANG08], the (math image) decreases with increasing . The decrease is thereby due to the decrease of the active CP energy region as given in (1.4).

Consequently, also for SiC-MOSFETs it is beneficial to perform CP experiments at the lowest possible temperature to maximize the active (math image) . The increasing energy range is also visible by an analysis of the dependence of the CP flat-band and threshold voltages on the chuck temperature as shown in Fig. 6.19.

The difference between (math image) and decreases with increasing temperature, again similar to Si based MOSFETs [Gro+84; ANG08].

For the sake of completeness, also the dependence of (math image) on the rise and fall times for different temperatures is shown in Fig. 6.20 and Fig. 6.21, respectively.

The number of charges pumped per cycle is fairly independent of the rise time for the whole investigated temperature range from −60 °C to 205 °C. From this follows that the density of interface traps is uniformly distributed in the lower half of the band-gap. In contrast, the increase of (math image) with decreasing fall time, which was already evident for the 30 °C measurement in Fig. 6.17, is even larger for −60 °C. This indicates a large density of interface traps close to the conduction band edge [Gro+84], consistent with other results based on CV measurements [Cio05; Roz08; Est11].

6.2.3 Parasitic substrate current

Earlier publications reported a large geometrical component which interferes with the CP current and makes the technique less reliable [SM98; Oka+08a; KTL96]. On a few of the SiC devices investigated in this thesis, which have not been optimized for CP measurements, a geometrical component was observable as well. This effect is visible as a substrate current on nMOSFET devices as shown in Fig. 6.22.

The current has a polarity which indicates that electrons are injected from the substrate towards the p-well of the nMOSFET. The current dependents strongly on the base and peak times of the pulse (not shown). A possible reason for the occurrence of the substrate current could be a large density of traps in the space charge region between the p-well and the substrate. However, this effect has vanished with a re-design of the test structures where the following was ensured:

• The p+ contact of the p-well was positioned as closely as possible to the channel such that the low conductive p-well has less impact.
• The p-channel implantation of the device was optimized for a homogeneous ion depth distribution.
• The metal contact to the gate poly was improved to ensure a low ohmic connection to the gate such that the pulse signal reaches the gate to the largest possible extent.