Degradation of Electrical Parameters of Power Semiconductor Devices – Process Influences and Modeling

Chapter 1 Introduction

The present thesis is based on the excellent work of many researchers who dealt with the reliability of metal oxide semiconductor (MOS) devices during the last five decades. In the following a rough and short overview of the literature which was of particular interest for the results of the thesis are summarized. The following compilation is not complete and only introduces a few of the concepts used in this thesis.

1.1 Degradation mechanisms and their characteristics

Based on previous work on possibly lifetime limiting effects in MOS field effect transistors (MOSFETs) [Sch06], a separation of degradation mechanisms into a few mechanisms can be performed. Only two of them, which are of particular importance in this thesis, are presented here.

1.1.1 Bias temperature instability

The positive or negative bias temperature instability (BTI) has become the most prominent degradation mechanism during the last couple of years, limiting the reliability of state-of-the-art MOSFETs in the whole application range from deca-nanometer sized devices for fast switching of low currents [TL+11b; Fra+12; Lee+13] to millimeter sized power devices which are capable of switching several Amperes [Are+08]. BTI occurs through the application of positive or negative voltage at the gate with respect to all other terminals of the device at elevated temperatures as 50 °C to 200 °C. The mechanism is temperature activated, meaning that higher temperatures increase the magnitude of the degradation [GN66; MM66]. The measurable result of bias temperature stress (BTS) is a reduction of the drain current due to a shift of the threshold voltage (math image) and a reduction of the channel mobility [GN66; MM66; JS77; Kac+08]. Negative BTI (NBTI) is more severe in p-channel MOSFETs (pMOSFETs) where it shifts the towards larger negative values, indicating the creation of positive charges close to the semiconductor-insulator interface [AM05; HDP06; Sch07]. Consistently, the application of positive bias at the gate causes an accumulation of electrons at the semiconductor-insulator interface which typically results in a (math image) shift towards more positive values, indicating the creation of negative charges.

BTS may occur due to biasing of the device close to or above the maximum operation voltage range, during operation of the device at elevated temperatures or because of combinations of both. The magnitude of the degradation measured by the shift of the threshold voltage (math image) varies approximately as a power of the stress duration [JS77].

1.1.2 Hot carrier degradation

When a MOSFET is operated with a voltage across source and drain, the carriers in the channel of the device are accelerated by the lateral electric field. For increasing source drain bias, the kinetic energy of the carriers eventually becomes sufficiently large to overcome a potential barrier for the activation of point defects close to the semiconductor-insulator interface [Sch06]. These point defects act as charges at the interface and interfere with the performance of the device. The term hot thereby indicates the large kinetic energy of the carriers. Similarly to BTI, hot carrier degradation (HCD) is observable as a decrease of the drain current due to a shift of the threshold voltage (math image) and a decrease of the mobility [Sch06; RR10; BH10; TG12].

The degradation is usually most efficient at positions along the channel where the carriers have the largest kinetic energy. This causes a strong localization of the created damage near the drain side of the MOSFET [TG12]. The high energetic carriers may also cause impact ionization close to the drain of the MOSFET [Sch06; TG12]. If the creation of an electron-hole pair through impact ionization occurs within the volume of the space charge region of the drain-body diode of the MOSFET, the electric field of the space charge region separates the pair. This leads to an impact ionization induced current between the body and the drain of the MOSFET [BH10]. For a fixed drain bias, the body current increases with increasing gate voltage up to a maximum point, where the mechanism is most efficient, before it decreases as the transistor enters its linear region [Sch06]. This peak in the body current occurs for silicon (Si) devices with a channel length in the micrometer range at a gate voltage of $\gls {Vg}= 1/\alpha \times \gls {Vd}$ with $\alpha =2$ – $3$ [BH10]. The biasing for the maximum of the body current is also considered to be efficient for HCD [TG12].