Degradation of Electrical Parameters of Power Semiconductor Devices – Process Influences and Modeling
Chapter 2 Impact of the gate bias polarity on BTI
The application of positive or negative BTS to a p- or n-channel MOSFET degrades the transistor to a certain amount. The most pronounced instability, however, occurs in pMOSFETs subjected to negative BTS [Sch07; HDP06; MKA04; Pob+11a]. Because of this, the negative BTI has been studied extensively in the literature and numerous physical degradation models have been proposed. However, for a few applications, especially for an nMOSFET as a power switch, only positive but no negative BTS is possible during device operation. Due to the effect of the bias polarity on the type of majority carriers at the interface – during NBTS holes and during positive BTS (PBTS) electrons, respectively – one would expect different microscopic processes to occur which cannot be covered by the models for NBTI alone. Consequently, it is important to understand the exact differences in the degradation behavior for n- and pMOSFETs following N- and PBTS [Pob+11a].
2.1 Impact of the gate poly doping type
For investigations of the impact of the bias polarity on BTI it is important to consider also the doping type of the polycrystalline silicon (poly) gate. The doping type changes the flat band voltage of the device and therefore impacts the oxide field value for a given stress gate voltage. It is further speculated to have an impact on the inherent degradation mechanism [Aba+93]. Additionally, the gate poly doping type can act as a source of charge carriers, namely electrons and holes, which can participate in the microscopic degradation mechanism.
In Fig. 2.1 the band structures of pMOSFETs during BTS with either n 
or p gate poly doping are sketched.
and p doped poly gate pMOSFETs and negative/positive BTS [Pob+11a]. Approximations for the splitting of the gate bias 
between the oxide and the semiconductor are given, where 
is the band gap energy of Si.
Additionally, equations derived from various approximations for the field across the oxide and the semiconductor for the stress bias are given in Fig. 2.1. In
particular it is assumed that the oxide and the interface are charge-free, the gate poly is not depleted, the quantum confinement of the carriers of the channel can be neglected, and that the semiconductor bands are bended exactly to intersect with
the valence and conduction band edges (Fermi level pinning). With the equations of Fig. 2.1 the appropriate gate voltages for a target oxide field can be
estimated with sufficient accuracy for the present purpose. The gate voltage for n poly gated nMOSFETs are calculated in analogy. A possible voltage across the gate poly [SKH93] is not considered due to the
high doping of the gate of about 1019/cm3.
The devices used in this work are fabricated using complementary MOS (CMOS) technology (n gated nMOSFETs and p gated pMOSFETs) and an n poly gated technology (both n- and pMOSFETs). The last combination, an nMOSFET with a p poly gate, is missing. However, this does not affect the main conclusions since the available combinations are sufficient to reconstruct the presumable result of the missing device.
To fully understand the impact of the gate poly doping type in detail, devices with different oxide thicknesses were used for the investigation of the impact of the distance between the gate poly and the active device interface.