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7.3.1 Plug-Fill Process

CVD of tungsten at a pressure of 60 Torr and a temperature of 703 K has been applied to an interconnect plug-fill process. A typical process sequence therefor comprises ${\rm Ti}$ PVD adhesion and ${\rm TiN}$ PVD barrier layers, a W CVD nucleation layer formed by silane reduction of ${\rm WF\hspace*{-0.2ex}_6}$ in presence of hydrogen, and tungsten bulk deposition with hydrogen reduction of ${\rm WF\hspace*{-0.2ex}_6}$. Since this work is focused on the final topography with special attention to the formation, size, shape, and location of voids, adhesion is considered to be sufficient and the four steps are combined to a two step sequence with a ${\rm TiN}$ PVD step followed by tungsten bulk CVD.

Figure 7.6: Tungsten deposition in a rectangular via for different time-steps (from left to right). The topmost line depicts the volume meshes used for the diffusion simulation with the resulting ${\rm WF\hspace*{-0.2ex}_6}$ distributions, below are the corresponding film topographies for an off-center position. The bottommost line shows the symmetrical profile evolution for the same initial geometry at a center wafer position.

Fig. 7.5 shows the profile evolution for the tungsten CVD step for a radially symmetric via at a center wafer position. For demonstration purposes the parameters for the reaction rate were artificially increased in order to reveal the non-conformal films arising from the depletion of ${\rm WF\hspace*{-0.2ex}_6}$ within the feature. Fig. 7.5(a) depicts the ${\rm TiN}$ PVD barrier layer over the initial geometry. According to the center wafer position for the ${\rm TiN}$ sputter deposition the distribution of particles arriving at the wafer surface is radially symmetrical, which leads to a radially symmetrical ${\rm TiN}$ layer. In the following CVD simulation carried out with iterative surface extraction [Fig. 7.5(b)], mesh generation [Fig. 7.5(c)], and diffusion/reaction simulation [Fig. 7.5(f)] this symmetry is maintained [Fig. 7.5(e)]. The final geometry for the cylindrical via with a diameter of 0.3 $\mu\mathrm m$ [Fig. 7.5(d)] contains a void whose top is significantly above the initial wafer surface approximately at the height of the ${\rm TiN}$ layer surface.

Fig. 7.6 illustrates the profile evolution for the same conditions for a rectangular via at different positions on the wafer. Fig. 7.6(e) to Fig. 7.6(h) show a sequence of time-steps for a peripheral wafer position. The corresponding volume meshes and ${\rm WF\hspace*{-0.2ex}_6}$ distributions are given above [Fig. 7.6(a) to Fig. 7.6(d)]. Fig. 7.6(i) to Fig. 7.6(l) denote the center position for the same process parameters. In the case of the peripheral position the time-step from Fig. 7.6(g) to Fig. 7.6(h) leads to the closure of the void. Since the fronts in Fig. 7.6(g) almost collide, the time-step control admits only a very small time-step leading to proper void closure in Fig. 7.6(h). This can be observed in the smaller increase in the wafer surface layer thickness between Fig. 7.6(g) and Fig. 7.6(h) with respect to the increase between Fig. 7.6(f) and Fig. 7.6(g).

Due to the different geometric conditions for the sputter deposition of the ${\rm TiN}$ layer, size and shape of the voids vary according to the resulting irregularity of the underlying PVD layers. Not only does the profile of the PVD layer depend on the initial geometry but also on the orientation of the structure with respect to the main particle flux. For the profiles of rectangular or elliptic vias it makes a major difference whether the main particle flux in the sputter deposition is parallelly or perpendicularly aligned to the structure.

In the presented simulations the variations in the void geometry originate from the position dependent flux variations in the PVD step. The conditions for the tungsten CVD layer are sufficiently homogeneous across the wafer. Hence, the variations in the underlying asymmetric PVD layers are continued throughout the CVD layer and underline the necessity of the rigorous three-dimensional approach for the CVD model.

Within the complete device manufacturing process the topmost position of the void is of special interest. In the considered simulations this position in the rectangular via (Fig. 7.6) is lower than in the circular via (Fig. 7.5) and even lower for the off-center position of the rectangular via. Additionally the void formed at the off-center position is shifted away from center of the via.

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