7.6.3 Technology G: Enhancement Type Metamorphic HEMT on GaAs

For digital applications an enhancement type InAlAs/InGaAs HEMT is developed for a gate length between ${\it l}_{\mathrm{g}}$= 150 nm and 70 nm. Fig 7.44 shows the simulated and measured transfer characteristics of the device with ${\it l}_{\mathrm{g}}$= 150 nm. Modeling of the device in good agreement with measurement data is possible. The difference of the ${\it V}_{\mathrm{DS}}$ voltage for the bias can be precisely fit. This precision is necessary to evaluate the capacitances ${\it C}_{\mathrm{gs}}$ and ${\it C}_{\mathrm{gd}}$ as a function of bias. In  (4.29) in Chapter 4 an integral is evaluated to calculate a speed relevant average value of the capacitances ${\it C}_{\mathrm{gs}}$ and ${\it C}_{\mathrm{gd}}$ for the voltage sweep in a digital application. This quantity can be extracted from device simulation, and thus variations of the physical parameters be evaluated based on the agreement given in Fig. 7.44. Fig. 7.45 shows the calculated reduction of ${\it C}_{\mathrm{gd}}$ a function of the relative dielectric constant of the passivation. Two gate shapes are considered: Gate shape 1 supplies an estimate of an average gate shapes during production, while Gate shape 2 simulates a very steep gate stem with reduced contributions to ${\it C}_{\mathrm{gd}}$, as was shown for pseudomorphic HEMTs in [50].

Figure 7.44: Transfer characteristics of an enhancement-type InAlAs/InGaAs HEMT for two $V_{DS}$ bias.

Figure 7.45: $C_{gd}$ reduction of a $l_g$= 150 nm HEMT versus average $eps_r$.

Figure 7.46: Threshold voltage $V_T$ versus gate-to-channel separation $d_{gc}$.

Figure 7.47: Threshold voltage $V_T$  versus $\delta$-doping concentration.

Variations of the threshold voltage ${\it V}_{\mathrm{T}}$ are very important to estimate and control for digital applications in order to achieve defined off- and on-switch-states in circuits during operation. Fig. 7.46 shows the simulated and measured dependence of ${\it V}_{\mathrm{T}}$ on the gate-to-channel separation ${\it d}_\mathrm{gc}$ relative to the nominal value of ${\it d}_\mathrm{gc}$ for a ${\it l}_{\mathrm{g}}$= 100 nm InAlAs/InGaAs device. The dependence of $\Delta{\it V}_{\mathrm{T}}$/ $\Delta{\it d}_\mathrm{gc}$ is found to be about -80 mV/nm for the device investigated.

To obtain an enhancement type HEMT for such high frequency of operation, a very delicate balance of $\delta$-doping concentration, gate-to-channel separation ${\it d}_\mathrm{gc}$, and distance of $\delta$-doping to channel is analyzed. Fig. 7.47 shows the dependence of ${\it V}_{\mathrm{T}}$ on the $\delta$-doping concentration introduced by MBE growth for an otherwise constant device. For concentrations taken from the linear range of Fig. 3.24 complete activation of the added donors is assumed. Fig. 7.48 shows the simulated and measured ${\it f}_\mathrm{T}$ for ${\it V}_{\mathrm{DS}}$$\leq$ 1 V for a device with ${\it l}_{\mathrm{g}}$= 150 nm. The agreement in this bias range requires a detailed analysis of the ohmic contact situation to model the linear region of the device. Due to the geometry (cap thickness) and the alloying process, contact Case I from Fig. 3.25 can be assumed in the simulation. Between simulations and measurements good agreement is achieved. As can be seen in Fig. 7.48, ${\it f}_\mathrm{T}$ as a function of ${\it V}_{\mathrm{DS}}$ bias rises stronger than linear to the maximum value for constant ${\it V}_{\mathrm{GS}}$.

Figure 7.48: $f_T$ versus $V_{DS}$ in the low-power range.

Figure 7.49: $f_T$ versus gate length $l_g$.

Finally, Fig. 7.49 shows the simulated and measured ${\it f}_\mathrm{T}$ versus gate length ${\it l}_{\mathrm{g}}$. The scaling is performed without decreasing the gate-to-channel separation ${\it d}_\mathrm{gc}$ lower than ${\it d}_\mathrm{gc}$$\geq$ 8 nm to control-gate-currents. Considering both yield and statistical variation, this represents a lower bound for the mean value, since assuming a standard deviation of 1.5 nm, as estimated from threshold variations ${\it V}_{\mathrm{T}}$, ${\it d}_\mathrm{gc}$= 10 nm is the lower bound of the on-wafer average value.