4.7 Delay Time Extraction for High-Speed Digital HEMTs

For next generation chip components for long range optical data transmission at data rates beyond 40 Gbit/s, i.e. 80 Gbit/s and 160 Gbit/s, high speed HEMTs face extremely high-speed requirements. For the technologies to develop, it is still not finally resolved, which figures of merit are to be optimized in order to ensure reliable operation for such high speed.

The quantities to evaluate speed and delay times can be taken both from analog and from digital RF optimization procedures. Next to the analysis of ${\it f}_\mathrm{T}$ and ${\it f}_\mathrm{max}$, which are purely analog quantities and deliver only qualitative estimates for speed in digital application, in a third approach delay times from ring oscillators can be used [5]. A fourth methodology to define delay times in digital devices is described in [241] by a transfer analysis of inverters. Table 4.5 summarizes the different delay times:

Table 4.5: Different definitions of delay times and extraction procedures.

Delay	Source	Origin	References
$\tau_{{\it f}_\mathrm{T}}$	1/ ${\it f}_\mathrm{T}$	analog h $_\mathrm {21}$	[23,196]
$\tau_{{\it f}_\mathrm{max}}$	1/ ${\it f}_\mathrm{max}$	analog MAG/MSG	[23,196]
$\tau_\mathrm {ring}$	ring oscillator	digital signal delay time	[5]
$\tau_{trans}$	inverter in source coupled FET logic	transfer function	[241]

The crucial difference between analog and digital applications is the dynamic ${\it V}_{\mathrm{DS}}$ bias for the digital case, which challenges the capabilities of the HEMT as a low voltage high-speed device. A very strong burden for both approaches is the careful inclusion of the parasitic elements. For digital HEMTs this concise inclusion is rendered complicated since the layout of a digital transistors varies much stronger than an analog one, and the characterization needs several test structures to evaluate parasitic delay times.

For the evaluation of HEMTs for 80 Gbit/s or even 160 Gbit/s circuit applications two of the four methodologies are further explored. They define an upper and a lower limit for the device speed required. The parameters obtained by both approaches are analyzed regarding their feasibility in device manufacturing. The first approach assumes the following rule of thumb for process safe operation: At a data rate of x Gbit/s a delay time of 2$\times$x GHz ${\it f}_\mathrm{T}$ at the reference plane is mandatory. This is less than demanded (x=4) in [87], but was found sufficient for 40 Gbit/s applications. Starting from (4.11) a total delay time $\tau_G$ is defined:

$$\tau_G = \tau_\mathrm {i} + {\it\tau}_{\mathrm{cap}}$$ (4.25)

${\it\tau}_{\mathrm{cap}}$ is the capacitive delay time due to ${\it C}_{\mathrm {IN}}$ and ${\it C}_{\mathrm{pgd}}$. The inductive contributions are considered constant for all transistors. The intrinsic delay time obtained from (4.11) then reads:

$${\it\tau}_{\mathrm{i}} = 1/{\it f}_\mathrm{T} =\frac {[{\it C}_{\... ...{\mit g}_{\mathrm{mi}}} = \tau_\mathrm {D} + \tau_\mathrm {G} +\tau_\mathrm {S}$$ (4.26)

The split into the three intrinsic delay times at drain, source, and gate was suggested by Nguyen in [196]. Table 4.6 summarizes a set of device parameters that fulfill the needs for 40 Gbit/s and 80 Gbit/s operation according to this methodology, further called Methodology I.

Table 4.6: Delay times and transistor parameters for Methodology I, given scaled to the gate-width and for a 10 $\mu$m gate-width HEMT.

Rate	${\it f}_\mathrm{T}$	${\it C}_{\mathrm {IN}}$+ ${\it C}_{\mathrm{pgd}}$	${\it\tau}_{\mathrm{i}}$	${\it C}_{\mathrm{gs}}$	${\it C}_{\mathrm{gd}}$	${\mit g}_{\mathrm{mi}}$	${\it R}_{\mathrm{S}}$	${\it R}_{\mathrm{D}}$	${\it g}_{\mathrm{ds}}$
Gbit/s	GHz	fF/mm	ps	fF/mm	fF/mm	S/mm	$\Omega\cdot$ mm	$\Omega\cdot$mm	mS/mm
		fF		fF	fF	mS	$\Omega$	$\Omega$	mS
40	87	100	10.8	1600	280	1.4	0.35	0.35	55
		1		16	2.8	14	35	35	0.55
80	173	100	5.2	900	230	1.8	0.35	0.35	75
		1		9	2.3	18	35	35	0.75

Using the second methodology further called Methodology II by [241] the delay times to achieve for a current switch, further called (CS), and source follower (SF) are given in (4.27) and  (4.28), respectively.

$${\it\tau}_{\mathrm{CS}} = \frac{{\it C}_{\mathrm{gd}}}{{\mit g}_{\mathrm{m}}}+\frac{{\it R}... ...{ds}}}+{\it R}_{\mathrm{G}} \cdot ({\it C}_{\mathrm{gs}}+{\it C}_{\mathrm{gd}})$$ (4.27)

$${\it\tau}_{\mathrm{SF}} = {\it C}_{\mathrm{gd}}\cdot ({\it R}_{\mathrm{L}}+ {\it R}_{\mathr... ...rm{ds}}+ \frac{1}{{\it R}_{\mathrm{S}}}}-\frac{1}{{\mit g}_{\mathrm{m}}} \bigg]$$ (4.28)

$$+ \frac{{\it C}_{\mathrm {L}}+ {\it C}_{\mathrm{ds}}}{{\mit g}_{\mathrm{m}}+{\it g}_{\mathrm{ds}}+\frac{1}{{\it R}_{\mathrm{S}}}}$$

The average for the capacitances $C_{\mathrm {gi}}$ can be obtained by numerical integration as given in (4.29), or by measured mean values, which are given in Table 4.7. In (4.29) $\phi$ represents the built in potential of the semiconductor, $C_{gi0}$ a zero bias capacitance, and the $V_{gi,i}$ lower and upper bounds for the voltages applied [242].

$$C_{\mathrm {gi}} = \frac{ \int_{V_{gi1}} ^{V_{gi2}} C_{gi0} ( 1- \frac{V}{\phi}) ^{-m} dV} {V_{gi2}-V_{gi1}}+ C_{pgi}$$ (4.29)

The load impedance ${\it C}_{\mathrm {L}}$ is determined to be:

$${\it C}_{\mathrm {L}} = {\it C}_{\mathrm{gs}}+ \bigg(1+ \frac{{\m... ...}{1+{\it R}_{\mathrm{L}}{\it g}_{\mathrm{ds}}}\bigg)\cdot {\it C}_{\mathrm{gd}}$$ (4.30)

Table 4.7 shows transistor parameters used and obtained by this methodology for a 10 $\mu$m HEMT for the source follower (SF) and the current switch (CS).

Table 4.7: Delay times for different components according to Methodology II  [241].

Rate	${\it R}_{\mathrm{L}}$	${\it R}_{\mathrm{G}}$	${\it C}_{\mathrm{gd}}$	${\it C}_{\mathrm{gs}}$	${\it C}_{\mathrm{ds}}$	${\it C}_{\mathrm {IN}}={\it C}_{\mathrm{pgd}}$	${\mit g}_{\mathrm{m}}$	${\it R}_{\mathrm{S}}$	${\it g}_{\mathrm{ds}}$	${\it C}_{\mathrm {L}}$	$\tau$
Gbit/s	$\Omega$	$\Omega$	fF	fF	fF	fF	mS	$\Omega$	mS	fF	ps
40 SF	400	0.1	2.8	12	2.6	0.5	14	35	0.55	27.65	3.99
40 CS	400	0.1	2.8	12	2.6	0.5	7	35	0.55	21.22	5.25
80 SF	400	0.1	2.3	6.75	1.5	0.5	18	35	0.75	21.4	2.46
80 CS	400	0.1	2.3	6.75	1.5	0.5	9	35	0.75	15.4	3.04

As expected, the values suggested by Methodology II are shorter than the delay times based on pure analog considerations for the same transistor in comparison to Methodology I. So when using Methodology I for estimates, it supplies a minimum requirement, but it is not ensured that twice the ${\it f}_\mathrm{T}$ value will support the necessary speed. Methodology II is more realistic with respect to the application and needs to be applied to compare the resulting delay times with the circuits needs. As also Methodology II is based on small-signal elements, it can be used for optimization. The estimates for 160 Gbit/s operation are not given in these calculations, since they are found to be speculative. By using either small-signal analysis for the analog delay with ${\it f}_\mathrm{T}$ or mixed-mode device simulation [106] both quantities can be extracted.