5.4 Modeling Integrated Circuits

A single monolithic simulation of multiple devices which are present in an integrated circuit is very difficult and reaches to the limits of currently available computers. Nevertheless, it is sometimes necessary to simulate at least some of these devices simultaneously. With SIESTA this can be done by using simulation-flow-models in conjunction with a network-model. Figure 5.5 and its associated description Example 5.6 demonstrate how a simulation-flow-model is modified by means of default overloading in order to produce devices resulting from different mask sets.

As results of the simulation-flow-model named pmos, nmos, and bipolar, we derive three descriptions of semiconductor devices. Additional to these device descriptions, we derive the capacitances of the interconnect networks which are present in the integrated circuit, from the model named cap. In the following we are able to carry out a circuit simulation using the mixed mode simulation features of MINIMOS-NT [22,5]. Thus, we are able to model distinguished devices of the integrated circuit simultaneously and can derive characteristics of the integrated circuit rather that just of one of its devices. Moreover, we are able to include interconnect capacities into this circuit, which can for example be modeled by a highly specialized simulation tool like SCAP [49,73]. As a result, we derive an elaborate model of an integrated circuit taking several devices as well as their interconnect networks into account.