3.1.5 Gate Delay

In addition to the transistors' properties and interconnect capacitances the gate delay depends on the circuit technique and on the average fan-in/fan-out . Unfortunately, the relation between these quantities and is anything but simple. Worse yet, simple equations like, e.g., the ones given in [87] and [5] can deviate considerably from the actual values.

Compact estimates of the gate delay in terms of the inverter delay and the average fan-in/fan-out can be derived for the main logic styles, i.e., circuit techniques (cf. Section A.2.3). Simple estimates, which assume a resistor network with all capacitors at the gate inputs, are $\ensuremath{t_{\mathit{g}}}\xspace = \ensuremath{t_{\mathit{i}}}\xspace \ensuremath{F_{\mathit{io}}}\xspace ^2$ for unbuffered static-CMOS gates, $\ensuremath{t_{\mathit{g}}}\xspace = \ensuremath{t_{\mathit{i}}}\xspace (\ensuremath{F_{\mathit{io}}}\xspace + 1)$ for buffered static-CMOS gates, and $\ensuremath{t_{\mathit{g}}}\xspace = \ensuremath{t_{\mathit{i}}}\xspace (\ensuremath{F_{\mathit{io}}}\xspace /2 + 1)$ for buffered dynamic-CMOS gates. These expressions are essentially equivalent to equations given in [87] and [5] with the same drawbacks. A more accurate expressions for the gate delay can be obtained by partitioning the transistor capacitances between the source and drain nodes. For static CMOS (cf. Fig. A.14) this yields

$$\ensuremath{t_{\mathit{g}}}\xspace = \frac{\ensuremath{t_{\... ...ace +2+\frac{6}{\ensuremath{F_{\mathit{io}}}\xspace } \right] .$$ (3.8)

Circuit simulations showed that this expression is accurate to 30% at supply voltages down to 0.2V.

A more pragmatic approach to gate delay estimation is based on the fact that, regardless of the particular logic style, a product-like logic block (cf. Section A.2.2.2) behaves like a distributed RC line. Consequently, a quadratic term of must be present in the gate delay for all logic styles, so that a polynomial function is assumed, which can be fitted to data from circuit simulations or measurements:

$$\ensuremath{t_{\mathit{g}}}\xspace = \ensuremath{t_{\mathit... ...}}\xspace + a_2\ensuremath{F_{\mathit{io}}}\xspace ^2 \right] ,$$ (3.9)

where the coefficients a_i depend on the logic style and to some lesser extent on the technology, supply voltage, and interconnect capacitance. The coefficients obtained from circuit simulations of NAND gates in a $\rm0.13\mu m$ CMOS technology are listed in Table 3.1. The values are the averages for $\ensuremath{F_{\mathit{io}}}\xspace =1\ldots5$, $\ensuremath{C_{\mathit{L}}}\xspace = 0\ldots\rm 40fF$, and $\ensuremath{V_{\mathit{DD}}}\xspace =0.4V$. As a good rule of thumb which also holds for all cases investigated in this work, the gate delay in a typical circuit can be assumed as

$$\ensuremath{t_{\mathit{g}}}\xspace (\ensuremath{F_{\mathit{io}}}\xspace =3) \approx 3 \ensuremath{t_{\mathit{i}}}\xspace .$$ (3.10)

Table 3.1: Polynomial coefficients for (3.9) (average values)

logic style	a0	a1	a2
static CMOS	0.35	0.55	0.10
buffered static CMOS, $\ensuremath{C_{\mathit{L}}}\xspace =0$	0.69	1.30	0.15
buffered static CMOS, $\ensuremath{C_{\mathit{L}}}\xspace >\rm 20fF$	0.10	0.67	0.06