Many of the above parameters depend not only on the
device
but also on the the logic style, i.e., the circuit design used to
implement certain logic functions, and on the type of system and its
operating modes.
In the following a homogeneous systems model is assumed, i.e.,
the values of
and
are average values.
Dynamic power consumption is proportional to
by a factor
,
the activity ratio.
When a gate is not switching, i.e., none of its inputs changes the
state, there should be no dynamic power consumption. While this is
true for static-logic gates, this is quite different in dynamic-logic
designs (see Section A.2.3.2): The output is continually
precharged and discharged, even when the gate input does not change.
Therefore, the effective
is higher for dynamic logic than
for static logic performing the same function.
Additional causes of an increased activity ratio are so-called glitches,
i.e., spurious transitions during the switching of a logic circuit
before it reaches a stable state [12,41].
Static power consumption is proportional to
by a factor
,
the leakage ratio. This parameter depends on the logic style as
this determines the average drain-source voltage of a transistor in the
off-state.
For example, the transistors of a transmission gate
would, on the average, see only one half of the supply voltage, thus,
.
For the inverter in Fig. 3.3, on the other hand,
is one.
As a general rule, large-fan-in designs, pass-transistor logic, and
pass-gate designs result in a smaller leakage ratio.
Taking
results in an upper-bound estimate of
the leakage power.