3.2.1 Origins of Power Consumption

The basic equations for static and dynamic power consumption were given already in Chapter 2 to derive the Ultra-Low-Power strategies. This section reviews them and discusses the impact of circuit and system properties in more detail. Looking at plain physics there are three major contributions to the power consumption in digital CMOS circuits:

dynamic power consumption

which is due to the diabatic charging and discharging of the circuit's internal and external capacitances when the circuit is operating. The dynamic power consumption per transistor is

$$\ensuremath{P_{\mathit{dyn}}}\xspace = \ensuremath{{\mathit... ...C_{\mathit{L}}}\xspace \ensuremath{V_{\mathit{DD}}}\xspace ^2$$ (3.13)

where is the clock frequency, is the activity ratio, i.e., the probability for a transistor to switch during a clock period.

static power consumption

which is caused by the finite off-state current that flows through turned-off transistors from the supply rail to ground. The static power consumption power per transistor is

$$\ensuremath{P_{\mathit{stat}}}\xspace = \ensuremath{{\mathi... ...{I_{\mathit{off}}}\xspace \ensuremath{V_{\mathit{DD}}}\xspace$$ (3.14)

where is the leakage ratio, i.e., the percentage of the supply voltage which is the average of a turned-off transistor. ^3.2

short-circuit power consumption

which originates from the so-called crow-bar or inverter crow bar current that flows during a short time through the series connected transistors from the supply rail to ground The short-circuit power consumption power per transistor is

$$\ensuremath{P_{\mathit{sc}}}\xspace = \ensuremath{I_{\mathit{sc}}}\xspace \ensuremath{V_{\mathit{DD}}}\xspace /2 .$$ (3.15)

The inverter crow bar current depends largely on the design and operation of the circuit: the longer the rise and fall times are in comparison to the delay time , the larger will be. Usually, in a well-designed system the effect of is negligible.

Figure 3.3: A CMOS inverter with a capacitive load

The total power consumption per transistor is then the sum of all three contributions.

$$\ensuremath{P_{\mathit{tot}}}\xspace = \ensuremath{P_{\math... ...\mathit{dyn}}}\xspace + \ensuremath{P_{\mathit{stat}}}\xspace$$ (3.16)

For a system consisting of N transistors the power consumption would then be $\ensuremath{P_{\mathit{sys}}}\xspace = N \left< \ensuremath{P_{\mathit{tot}}}\xspace \right>$ In a typical digital CMOS VLSI system, like a microprocessor or a cache memory module, the dynamic power consumption dominates by far. The reason is that the threshold voltage is usually in the order of $0.5\ldots\rm0.8V$ ( $\approx20\ldots30\ensuremath{U_{\mathit{T}}}\xspace$) so that the contribution from the leakage current is also negligible.

Footnotes

... transistor.^3.2

In most cases is assumed to be 1 for simplicity.