The Physics of Non–Equilibrium Reliability Phenomena

Chapter 5 Modeling Results

In this Chapter the model approaches introduced in Chapter 4 will be applied to investigate the individual effects of HCD and non–equilibrium BTI. Together with an in–depth analysis the modeling frameworks and the respective results will be thoroughly tested and validated against a wide class of measurement sets. Subsequently, the first rigorous simulation study of a MOSFET in full {$V_{\mathrm{G}},V_{\mathrm{G}}$} bias space will be presented and analyzed. Furthermore, a particular experiment based on alternating stress sequences reveals the implications of different stress regimes onto the various types of defects. The presented studies will clearly reveal the conceptual limits of the assumption of independent descriptions of degradation regimes.

5.1 Hot–Carrier Regime

First, the modeling framework introduced in Sec. 4.1 will be challenged using two different types and technologies of devices, an nMOSFET and a pMOSFET with different gate lengths. This direct comparison was chosen due to occasional reports which show that the damage caused by HCD for nMOS devices is larger than for the pMOS counterparts [55, 56, 287, 288]. Note that the concept of resonance–induced excitations provides a physically meaningful explanation for this observation: If the accessible resonance state for holes is higher in energy than for electrons, ${ϵ}_{\mathrm{res},n}=3.64eV$ and ${ϵ}_{\mathrm{res},p}=3.96eV$ – as suggested by the ab initio results in Chapter 3 – it is less likely for holes to trigger bond excitation followed by the creation of interface defects.

5.1.1 Energy Distribution Functions

For the calculation of the carrier energy distribution functions (EDFs), which yield the information on how carriers are distributed over energy, the higher order spherical harmonics expansion simulator SPRING¹ has been used. The bipolar Boltzmann transport equation (BTE) was solved self–consistently on the calibrated 2D structures obtained from process simulations. The scattering mechanisms considered are acoustical and optical phonon scattering, impurity scattering as well as impact ionization with secondary carrier generation.

The results for two devices – a $65nm$ nMOSFET and a $100nm$ pMOSFET – and selected stress conditions are shown in Fig. 5.1. Clearly visible is the characteristic accumulation of highly energetic minority carriers at the drain end of the channel for both devices. As expected, increasing the stress conditions results in a more pronounced high energy fraction of the EDFs for holes (pMOS) and electrons (nMOS). However, while the EDFs of the secondary generated holes in the nMOS remain almost unchanged for the given stress conditions ($V_{\mathrm{G}}=V_{\mathrm{D}}$), the electron EDFs in the pMOS significantly change for higher stress bias. Thus, particularly for the highest drain bias conditions, $V_{\mathrm{D}}=\text{−}2.8V$, electrons can be expected to contribute to the total degradation in pFETs, since their EDFs are populated for energies up to $3eV$ along the channel region.

Influence of Temperature

In order to assess the reliability behaviour at elevated temperatures, the EDFs have been calculated at various temperatures, see Fig. 5.2, because the corresponding scattering rates are influenced by the lattice temperature, see [289]. Phonon and impurity scattering rates increase with $T$, via the occupation number for phonons given by the Bose–Einstein distribution and the screening length within the Debye formulation respectively, whereas the electron and hole II rates are assumed to be temperature independent and exclusively energy dependent. However, since phonon and impurity scattering at elevated $T$ modify the EDF, the II rates are also, therefore, indirectly affected. Thus, low and medium energy carriers which are determined by phonon and impurity scattering are suppressed at increasing temperatures, while the high energy tail, represented by the tail of a thermalized Maxwell–Boltzmann distribution, is enhanced. These characteristic features are well represented by the EDFs for both devices and two different temperatures ($T=298K$ and $T=398K$ for the pMOSFET and $T=348K$ for the nMOSFET, respectively) shown in Fig. 5.2.

5.1.2 pMOSFET versus nMOSFET

Measurements for the modeling benchmark have been performed on two different devices. A pMOSFET with a gate length of $100nm$ and an nMOSFET with a gate length of $65nm$, both technologies employing a $2.2nm$ SiON thick gate oxide and have an operating voltage of $|V_{\mathrm{DD}}|=1.5V$. The devices have been stressed at two temperatures, $T=298K$ as well as $T=398K$ for the pFET and $T=348K$ for the nFET, and were subjected to their respective nominal worst–case stress conditions, namely $V_{\mathrm{G}}=\text{−}1.5V$ and $V_{\mathrm{D}}=\text{−}1.8,\text{−}2.3$ and $\text{−}2.8V$ for the pMOS and $V_{\mathrm{G}}=V_{\mathrm{D}}=1.8,2.0$ and $2.2V$ for the nMOS device. To monitor the degradation trend $\mathrm{\Delta }{I}_{\mathrm{D},\mathrm{lin}}(t)$ traces up to $10ks$ of stress were recorded.

The calculated energy distribution functions are shown in Fig. 5.1 and explained in detail in the corresponding Section 5.1.1. Interface state profiles $N_{\mathrm{it}}(x)$ along the Si/SiON interface have been calculated using the model introduced in Sec. 4.1, and subsequently the degradation characteristics has been calculated using TCAD tools. In order to give detailed insights into the calculations and shed light into the degradation processes, Fig. 5.3 shows the rate matrix of one Si–H bond potential with 20 eigenstates localized in the left well along the channel for both devices. At the source side minority carriers – holes in the pFET and electrons in the nFET – are close to equilibrium, compare with Fig. 5.1 and Fig. 5.4, and thus are not able to scatter into an available resonance. The upper triangle of the matrix is, therefore, mainly determined by dipole induced excitations and the detailed balance condition at the given temperature. However, along the interface carriers are accelerated by the electric field and exchange energy via various scattering mechanisms, resulting in a non–equilibrium EDF with a substantial hot energy tail at the drain side. This enables the formation and transient occupation of an ionic resonance, allowing for multiple excitations shown as large off diagonal elements in the rate matrix. Furthermore, as already discussed above, the effect of impact ionization potentially aids the excitation and dissociation mechanisms via energetic secondary generated carriers. Whereas for the nMOS this component seems to be negligible, see the right panels of Fig. 5.3, secondary generated electrons in the pMOS seem to account for a major contribution to the overall excitations. Particularly in the channel region and towards the source side electrons up to $3eV$ and more are present, see Fig. 5.4, which are able to scatter into the available anionic resonance state.

The calculated $N_{\mathrm{it}}(x)$ profiles reflect the analysis regarding the rate matrix and excitation processes, see Fig. 5.5. Clearly visible are the characteristic peaks at the drain end of the channel for both, the n– and pMOS device, for all stress conditions. This particular feature of HCD can evidently be explained quite well by the hot carrier ensemble at the drain end, see Figs. 5.5 and 5.4. However, while for the nMOSFET and the given stress conditions the damaged region continuously extends from the drain towards the channel region, the buildup of a second peak in the channel area is visible for increasing $V_{\mathrm{D}}$ bias in the pMOS device. Together with the individual bond breaking rates ${\mathrm{\Gamma }}_{\mathrm{break}}$ for electrons and holes shown in the lower panels of Fig. 5.5, the EDFs in Fig. 5.4, and the rate matrix for the corresponding carriers in Fig. 5.3, a more detailed understanding of this behaviour can be established. Apparently, the degradation in the nMOS is exclusively determined by minority carriers, whereas in the pMOS a significant contribution is due to secondary generated electrons created by II.

There are two main reasons for this difference. First, the devices have been subjected to different stress conditions. The stress conditions $V_{\mathrm{G}}\sim 0.5V_{\mathrm{D}}$ for the pMOS have been chosen to represent the nominal worst–case conditions for long–channel devices which correspond to the maximum substrate current². Contrary, the nMOS device has been subjected to $V_{\mathrm{G}}=V_{\mathrm{D}}$ stress conditions correlating to the well known worst–case stress for short–channel devices. Second, and more important due to being a key ingredient in the modeling framework introduced in Sec.4.1 is the impact of different resonance states accessible for electrons and holes. The available scattering state for electrons is about $\sim 0.4eV$ lower in energy compared to the hole resonance. Moreover, the minimum of the potential energy curve for the excited anionic complex is shifted twice as much with respect to the ground state minimum compared to the cationic equilibrium position. Due to the overlap integral of the wavefunctions within the resonance mediated formulation, see (4.23), larger shifts enhance the probability of overtone transitions, see Fig. 5.3. Hence, electrons are more efficient in exciting and breaking the Si–H bond. This is particularly visible at the drain end of both devices. Although the energy distribution functions are comparable within this region, see Fig. 5.4 EDF${}_{\mathrm{e}}$ (nMOS) and EDF${}_{\mathrm{p}}$ (pMOS), the electron rates ${\mathrm{\Gamma }}_{\mathrm{break}}$ are almost two orders of magnitude larger, see Fig. 5.5. Furthermore, secondary generated holes in the channel region of the nMOS do not contribute to the creation of damage at all, while electrons generated by II rather dominate the degradation in the respective region within the pMOS.

Resonance based excitations not only provide a fundamental understanding of how carriers interact and eventually break Si–H bonds, but also allow for an accurate microscopic description which properly captures the degradation trends, see Fig 5.6.

A unique, albeit slightly optimized, parameter set has been used to describe HCD in both devices, see Fig. 5.7 and Table 5.1. All parameters are within a reasonable range and close to reported values in the literature and the DFT results presented in Chap. 3. Only two parameters are associated with a higher degree of uncertainty where solely the results presented within this thesis are available or literature values. First, the resonance width $\mathrm{\Delta }{ϵ}_{\mathrm{res}}$, which was calculated by Stokbro et al. to be $1eV$ for the anionic and $0.6eV$ for the cationic resonance state respectively [114, 115]. However, for a typical resonance lifetime of ${\tau }_{\mathrm{res}}=\hslash /\mathrm{\Delta }{ϵ}_{\mathrm{res}}\sim 1-2fs$, the width is about $0.2-0.7eV$ [236, 237, 276]. Second, the shift of the equilibrium position of the excited potential energy curves with respect to the ground state minimum. The calculations in Sec. 3.4 show a shift of $\sim 0.4a_0\sqrt{m}$ for the positively charged PEC and $\sim 0.9a_0\sqrt{m}$ for the negative PEC which served as an input for the model. Due to the amorphous interface an intrinsic variation of this quantity is, however, to be expected. Note that, in total 750 unique configurations with individual PECs and resonances have been used by randomly selecting uniformly distributed parameters of the model potentials, see Sec. 4.1.2. The resulting important values for the modeling framework are shown in Fig. 5.7 and listed in Tab. 5.1, termed as Full Model.

Furthermore, Table 5.1 also shows the parameter used with the Harmonic Model introduced in Sec. 4.1.7. In order to reduce the complexity and the computational requirements of the calculations, the simplified model focuses on the decisive parameters which control the reaction dynamics, namely $E_{\mathrm{B},\mathrm{f}}$ together with the angular frequency of the oscillator as well as the shift of the respective PECs, $\mathrm{\Delta }{q}_{\mathrm{e}/\mathrm{p}}$. Such approximations allow to place the Si–H bond configurations on a grid spanned by the three distributed parameters and effectively enables deterministic simulations. Nevertheless, the harmonic model matches the experimental data very well while maintaining a physically reasonable parameter set. Further information is given in [MJC5].

5.1.3 Elevated Temperatures

The impact of temperature onto the degradation due to hot–carriers is still not fully understood. Traditionally, in long–channel devices with the worst–case stress conditions being $V_{\mathrm{G}}\sim 0.5V_{\mathrm{D}}$, previous studies have shown that HCD is suppressed at elevated temperatures [290–292]. Quite to the contrary, an increasing temperature in short–channel devices, subjected to $V_{\mathrm{G}}=V_{\mathrm{D}}$ stress biases, typically results in an aggravation of HCD [55, 293, 294]. However, in a recent publication also the opposite trend has been reported [MJJ12].

Such, seemingly, ambiguous temperature trends stem from a complex interplay of various effects and processes together with a partly opposing influence of temperature. First, the implications on the transport properties itself. As shown above, see Fig. 5.2, the individual scattering rates are enhanced with temperature which decreases the population of low and medium energies. On the other hand, the high energy tail, which represents the thermalized carrier ensemble, is enhanced. Furthermore, the EDFs and the importance of low/medium and high energy carriers strongly depend on the device architecture and the applied bias conditions, which needs to be considered for the temperature behaviour of HCD. Second, the vibrational lifetime ${\tau }_{1,0}$ is a decreasing function with temperature, see Sec. 4.1.3, and therefore, represents a competing effect at elevated $T$. Third, a possible contribution of BTI and oxide defects, which is known to be strongly temperature accelerated. Due to the available defect bands this would particularly apply for negative bias temperature instability (NBTI) in SiO${}_2$ based pMOSFETs and PBTI in scaled nMOS transistors employing high–$\kappa$ gate stacks [MJJ7, MJJ8].

Both devices, the pMOSFET and the nMOSFET, have been stressed at elevated temperatures, $T=398K$ (pMOS) and $T=348K$ (nMOS), respectively. In order to exclude the third point, a concurrent contribution of BTI, the devices have been switched to recovery conditions after the stress sequence. Neither the n– nor the pMOS devices showed a noteable recovery of the measured parameters. The experimental data together with the simulation results are shown in Fig 5.8, where the data for $T=298K$ are marked as gray curves for comparison. One can clearly see an opposite temperature trend which is properly captured by the model. While for the pMOS an increasing $T$ results in a more pronounced damage due to hot–carriers, the degradation in the nMOS is suppressed. However, note that for the highest stress condition the effect of temperature almost vanishes in both devices.

The lower stress regimes chosen for the pMOSFET, $V_{\mathrm{G}}=\text{−}1.5V,V_{\mathrm{D}}=\text{−}1.8V$ and $V_{\mathrm{G}}=\text{−}1.5V,V_{\mathrm{D}}=\text{−}2.3V$, are actually dominated by the degradation due to holes within the drain region, see Fig. 5.5. At elevated temperatures the high energy ensemble is enhanced, aiding the overtone transitions and direct bond breaking process. Due to their small number of excitation steps, these processes depend only very weakly on the (decreasing) vibrational lifetime, resulting in an aggravation of HCD, particularly at short stress times. The most severe stress bias, $V_{\mathrm{G}}=\text{−}1.5V,V_{\mathrm{D}}=\text{−}2.8V$, on the other hand, is strongly affected by the presence of energetic electrons. The electron EDFs towards the drain end are slightly shifted towards higher energies at $T=398K$, see Fig. 5.2. However, this trend is compensates by the decreasing vibrational life ${\tau }_{1,0}$, resulting in virtually the same degradation behaviour as for $T=298K$.

The nMOSFET has been stressed at $T=348K$ which yields only minor differences in the calculated EDFs, see Fig. 5.2. Therefore, the overall degradation trend at the measured temperature is dominated by the reduction of the vibrational lifetime, resulting in a reduction of hot–carrier related degradation. Nevertheless, also for the nMOS a decreasing difference between the two temperatures is visible with increasing bias conditions. This is again due to the increasing importance and influence of the high energy tail at $V_{\mathrm{G}}=V_{\mathrm{D}}=2.2V$ where carriers are able to trigger, the almost lifetime independent, overtone excitations.

For all simulations the optimized parameter set presented in Table 5.1 has been used with a vibrational lifetime of ${\tau }_{1,0}=0.35ns$ at $T=348K$ and ${\tau }_{1,0}=0.28ns$ at $T=398K$, respectively.