model
Using the macromodeling task capabilities, an empirical model based on
MINIMOS simulation of 
is built. The model relates gate
capacitance at a specific set of voltage values to polysilicon gate length
and doping (
and 
).
The region of validity of the model covers the expected
range of and variation.
It was found that a linear polynomial model accurately mimics
MINIMOS in this restricted parameter space. Thus it could be used
in lieu of MINIMOS in the extraction technique. The model linearity makes
the and determination possible without the need to perform
a nonlinear optimization.
The linearized capacitance models is of the form:
where 
, 
and 
are the model parameters for the
th capacitance. Using vector and matrix notation this could be expressed as:
Where 
is a vector whose elements are the differences
and A is an 
matrix of the and
coefficients. This is an overdetermined linear system whose solution is:
Table 6.4: Values of the coefficient of the linear capacitance
expressions and the fit errors to MINIMOS calculated values at
of 2.0, 2.5, 3.0, and 3.5 Volts.
In Table 6.4 the coefficients equations for the linearized
capacitance at = 2, 2.5, 3 and 3.5 Volts are listed together
with the corresponding maximum and average percent errors between MINIMOS and
the linear models. As seen, the accuracy of the linear models is excellent.
Given a nominal device structure, and the expected range of variation
of and 
, the empirical model building task module and
MINIMOS could be used to generate the linear polynomials models. The
resulting model coefficients can then be used to compute
and from four capacitance measurements according to
(6.13). This procedure is very efficient and can be implemented
as part of a routine characterization procedure of intra-die length variation.
