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6.2 Design of Experiments

The input parameters, which are the technology parameters \ensuremath{L_{\mathit{nom}}}, \ensuremath{t_{\mathit{ox}}}, and \ensuremath{I_{\mathit{off,nom}}}, and the main operating parameter \ensuremath{V_{\mathit{DD}}} make up a parameter space which is sampled in the range of interest. Each sample, i.e., experiment, is characterized by the respective tuple of parameters. The set of experiments was chosen by a full-matrix design with parameter values from Table 6.1.


Table 6.1: Parameter values for the full-matrix set of experiments
parameter   values
\ensuremath{L_{\mathit{nom}}} [$\rm\mu m$] 0.18, 0.15, 0.13, 0.10, 0.07, 0.05, 0.035
\ensuremath{t_{\mathit{ox}}} [nm] 3.0, 2.0, 1.0, 0.6
\ensuremath{V_{\mathit{DD,nom}}} [V] 0.2, 0.5, 0.9, 1.2
\ensuremath{I_{\mathit{off,nom}}} [ $\rm A/\rm\mu m$] C-9, 10-8, 10-7, 10-6

The choices for \ensuremath{L_{\mathit{nom}}}, \ensuremath{t_{\mathit{ox}}} (1-3nm), and \ensuremath{V_{\mathit{DD,nom}}} (0.5-1.2V) were motivated by the SIA roadmaps of 1994/97 [3,4], whereas $\ensuremath{V_{\mathit{DD,nom}}}\xspace =\rm0.2V$ and \ensuremath{I_{\mathit{off,nom}}} stem from Ultra-Low-Power considerations. The gate oxide thickness of 0.6nm approximates the case, where a very thin high-permittivity gate insulator is used, so that the effective electrical oxide thickness is mainly determined by the quantization in the channel. This effect, which moves the peak of the carrier concentration 1...2nm away from the interface, can be roughly accounted for by a geometrical gate oxide thickness of $\ensuremath{t_{\mathit{ox}}}\xspace = {\rm 2nm} \cdot \ensuremath{\epsilon _{\mathit{s}}}\xspace /\ensuremath{\epsilon _{\mathit{i}}}\xspace = \rm0.6nm$.


next up previous contents
Next: 6.3 Evaluation and Optimization Up: 6. Constrained Optimization of Previous: 6.1 Device Structure Definition

G. Schrom