The input parameters, which are the technology parameters
,
,
and
,
and the main operating parameter
make up a parameter space
which is sampled in the range
of interest.
Each sample, i.e., experiment, is characterized by the
respective tuple of parameters.
The set of experiments was chosen by a full-matrix design with
parameter values from Table 6.1.
parameter | values | |
---|---|---|
![]() |
[![]() |
0.18, 0.15, 0.13, 0.10, 0.07, 0.05, 0.035 |
![]() |
[nm] | 3.0, 2.0, 1.0, 0.6 |
![]() |
[V] | 0.2, 0.5, 0.9, 1.2 |
![]() |
[
![]() |
C-9, 10-8, 10-7, 10-6 |
The choices for
,
(1-3nm), and
(0.5-1.2V) were
motivated by the SIA roadmaps of 1994/97 [3,4],
whereas
and
stem from Ultra-Low-Power
considerations.
The gate oxide thickness of 0.6nm approximates the case, where a very thin
high-permittivity gate insulator is used, so that the effective
electrical oxide thickness is mainly determined by the quantization
in the channel.
This effect, which moves the peak of the carrier concentration
1...2nm away from the interface, can be roughly accounted for
by a geometrical gate oxide thickness of
.