6.3 Evaluation and Optimization

The evaluation of the experiments was done with simple scripts which submit the experiments one by one to the performance metric software and collect the results afterwards. The results are all output parameters in Tables 3.4, and 3.5. The system parameters (cf. Table 3.2) were chosen according to a typical microprocessor. The data from the experiments table and the results are then combined to a complete table of tuples, which is then used as input for further postprocessing.

Table 6.2: System model parameter

parameter	value	remark
	7
	0.1
	1.0	inverter
	$0.2\rm fF/\mu m$
	200	typ. microprocessor
k1	1.0	PMOS equiv. to NMOS
k2	2.0
k3	0.9302	obtained from calibrating to circuit simulations

An excerpt from the data is shown in Figs. 6.2-6.5 (such plots can be generated automatically during and after the simulation process). Figure 6.2 shows the normalized noise margins and inverter gain for $\ensuremath{L}\xspace = \rm0.13\mu m$ and $\ensuremath{V_{\mathit{DD}}}\xspace = \rm 1.2V$ as a function of the gate oxide thickness, where the curve parameter is nominal off-state current. It can be observed that devices with $\ensuremath{I_{\mathit{off,nom}}}\xspace \ge\rm 100\mu A/\mu m$ and $\ensuremath{t_{\mathit{ox}}}\xspace =\rm0.6nm$ fail the noise margin criterion of 30% . Figure 6.2 shows the delay time and switching energy for the same case, where a gate oxide thickness below 1nm obviously cannot improve the performance. Figures 6.4 and 6.5 show the same data for $\ensuremath{t_{\mathit{ox}}}\xspace = \rm 2nm$ as a function of the supply voltage. What can be seen in Fig. 6.5 is a strong dependence of the switching energy on the supply voltage, whereas the increase of the delay time is only minor at higher leakage currents .

Figure 6.2: Qualification parameters vs.

Figure 6.3: Performance parameters vs.

Figure 6.4: Qualification parameters vs.

Figure 6.5: Performance parameters vs.

For the optimization of input (i.e. technology and operating) parameters according to a certain criterion for a given gate length a discrete optimization is done on the respective subset of the data, i.e., the best tuple according to the optimization criterion is selected. In order to achieve a finer resolution of the input parameter space the discrete optimization is done by sampling a suitable interpolation function of the data. In this example, cubic linear or logarithmic functions were used.

The reason for choosing a discrete-optimization algorithm is primarily the easier implementation of the non-linear constraints, which are imposed by the functional criteria. The constraints used in this example are listed in Table 6.3.

Table 6.3: Optimization constraints

	>	0.3	min. inverter normalized noise margins
	>	4	min. inverter gain
	<	$5\cdot10^{18}\rm cm^{-3}$	max. dopant level
${\ensuremath{V_{\mathit{DD}}}\xspace }/({\ensuremath{t_{\mathit{ox}}}\xspace +\rm0.6nm})$	<	$\rm 6MV/cm$	max. gate oxide field
$\sqrt{{2\ensuremath{q}\xspace \ensuremath{N_{\mathit{ch}}}\xspace (\ensuremath{... ...mathit{DD}}}\xspace +\rm 1.12V)}/{\ensuremath{\epsilon _{\mathit{s}}}\xspace }}$	<	$\rm 1MV/cm$	max. field in pn junctions
	<	$\ensuremath{t_{\mathit{d,ub}}}\xspace$	max. delay time (optional)
	<	$\ensuremath{E_{\mathit{s,ub}}}\xspace$	max. switching energy (optional)

Note, that is not a constraint, but a design parameter as mentioned earlier.

As a consequence of the discretization it may occur that two different optimization criteria result in the same optimum for a certain range of and yield different optima elsewhere. The interpolation reduces this effect but cannot completely eliminate it. Therefore, the resulting curves of some optimum as a function of the gate length may be somewhat bumpy. Furthermore, the various constraints may have a similar effect on the curves.