This introductory chapter gives an overview of both the history and importance of the semiconductor technology. The motivation for TCAD (technology computer aided design) and the importance of simulations are discussed. The different process steps used in the manufacturing of semiconductors are briefly presented. The importance of topography simulation is also discussed. Finally, this chapter concludes with an outline of this thesis.
During the human history, scientific and technological inventions have progressed considerably the type and the whole standard of living. In the last century the atom has been split into its components and the micro- and nano-technologies have been developed. Furthermore, machines have been invented that perform millions of computations per second. The most important common themes of the above mentioned advances are the electronic properties of materials, which show a richness of physical interactions dominating the modern life from household applications to global industries.
1947 Schockley, Bardeen, and Brattain invented the silicon-based transistor. This invention was the beginning of the semiconductor industry. Semiconductors provide a very good electronic control and thus they are the foundation stone of computer revolution. Soon after the transistor invention, many transistors were fabricated on a single chip. Since the production of the first IC (integrated circuit) in the late 1950s the number of components had been doubled yearly. This tendency was first predicted in 1964 by Gordon Moore who was a semiconductor engineer and a co-founder of Intel in 1968. His law was valid till the late 1970s as the doubling period was extended to 18 months and has remained up to now.
Although there are many problems to improve the integration factor per chip and to manufacture faster and smaller electronic devices, the demand is still increasing. The miniaturization and integration enable to use batch processing techniques that lead to cost reduction. For example, the computer revolution is the father of Internet which is continuously demanding an increase of information capacity and data bandwidth required for tele- and data-communication applications.
TCAD is widely used in the semiconductor industry to design and optimize transistors. With the increasing complexity of device structures and the assault of sophisticated diffusion mechanisms, separate process simulation investigations were developed independently to model the complete process flow from the silicon substrate to the passivation of the surface. It is the ultimate goal of TCAD to replace the experimental trial and error process with simulations to reduce capital outlay as well as to shorten the development cycle.
Process modeling and simulation have historically begun from stand-alone programs for single process steps, such as oxidation, lithography, ion implantation, diffusion, etching, deposition, and metalization. The goal of all of these simulators is to predict the different effects of each single process and to quantify the influence of the process parameters. Not already enough, these different simulators are combined to an integrated process simulation flow to follow the process steps applied in semiconductor manufacturing as closely as possible. The output of an integrated process simulator ideally results in a device representation which exactly mirrors the fabricated chip. This device representation can not only be used for device simulators but also for resistance, capacitance, and parameter extraction of interconnect lines. Therefore, the final simulation results also give insight into device characteristics which are hardly accessable to measurements.
Topography simulation plays the most important role in linking TCAD to the design and layout of IC s, which is realized with ECAD (electronic computer aided design) [59,64]. ECAD provides the tools necessary for the generation of a physical representation of the circuit diagram which is a symbolic description guaranteeing the complex functionality of the circuit required by the operational specifications of the customer.
Although costs have played an important role for the development of TCAD , it is wrong to see the costs exclusively as its reason. TCAD is also serving scientific interests in process and device physics by modeling and simulation.
Classical TCAD simulation tools solve PDE s (partial differential equations) within a specific macroscopic simulation domain. Common semiconductor manufacturing steps are simulated and modeled by continuum equations and numerical algorithms. The application of these TCAD simulation tools for reactor-scale simulation domains is limited by the number of required discretization points and subsequently by the speed as well as the available memory of computers nowadays. In order to link the reactor-scale simulations with the feature-scale simulation certain approximations have to be taken into account. Since the wafer size is increasing and the feature sizes are decreasing, the gap between reactor-scale and feature-scale simulations is growing with every new generation. This leads to the conclusion that reactor-scale simulations will play only a minor role for feature-scale simulations (cf. Chapter 4). Therefore, we limit ourselves to feature-scale simulations in this thesis.
This section provides an overview of the processing steps used to manufacture advanced electron devices.
Etching processes are used to partly remove material in order to create patterns to obtain the desired device or interconnect geometry. Particles in the etching component (a liquid or gas) remove material by attacking the exposed surface. The material may be removed isotropically, as often encountered in chemical or wet etching, or anisotropically for which dry or a plasma etching is used. In the case of a dry-etching process, the total etch rate consists of an ion-assisted rate and a purely chemical etch rate due to etching by neutral radicals which may still have a directional component. The total etch rate can depend on shadowing within the reactor and by the structures on the substrate itself, the angle-dependent flux distribution of particles from the reactor volume, the angle of incidence of the particles relative to the surface normal direction, reflection/re-emission of etching particles, and surface diffusion effects. RIE (reactive ion etching) provides high anisotropy which is achieved via different mechanisms by ions impinging onto the surface. The main advantage of RIE is its enhanced directionality compared to chemical etching. RIE becomes increasingly important as device sizes decrease substantially and etching must proceed even deeper in vertical direction without negatively affecting adjacent features.
Today's ULSI (ultra large scale integration) technology is to a large
extent based on the excellent properties of thermally grown silicon
dioxide layers. SiO
is used as gate dielectric in MOS (metal
oxide semiconductor) devices, as implantation or doping mask, and for device isolation purposes.
It has been proven by a number of experiments that thermal oxidation
of silicon proceeds by diffusion of the oxidant through the growing
oxide. The oxidation reaction itself takes place at the oxide-silicon
interface. During oxidation, the oxide-silicon interface moves into
the silicon material as the silicon is oxidized. Considering the
densities of silicon and of SiO,
it can be shown that a part of the oxide layer grows into the silicon
substrate. The remaining part grows on top of the silicon, resulting in a non-planar surface if oxidation is local.
. As
line widths continue to shrink below 0.18
, and as circuits become
more complex, the need for planarity becomes critical. Topological
imperfections adversely affect the lithographic process
that is used to etch the circuit patterns on the wafer (cf.
Section 1.3.5). As the number of layers increases, the
difficulty in maintaining the focus in the lithography processes
increases. The multiple metalization layers in today's devices require
extreme planarity to maintain high manufacturing yields. The CMP process enables the manufacture of these complex devices by polishing the surface of the wafer after each layer of the circuit is added. The resultant CMP waste stream contains suspended particles, dissolved metals, chemicals and other contaminants from the wafer and CMP slurry.
Lithography is the process of transferring geometric shapes on a mask to the surface of a silicon wafer. These shapes make up the parts of the circuit, such as gate electrodes, contact windows, metal interconnections, etc. The final IC is made by sequentially transferring the features from each mask, level by level, to the surface of the silicon wafer. An ion implant, oxidation, or metalization operation may take place between the successive image transfers.
In the IC lithographic process, a photosensitive polymer film is applied to the silicon wafer, dried, and then exposed to UV (ultraviolet) or other radiation with the proper geometrical patterns provided by a photo-mask. After exposure, the wafer is brought into contact, e.g., by dipping or spraying, with a solution that develops the images in the photosensitive material. Depending on the type of polymer used, either exposed (in the case of positive resists) or non-exposed (for negative resists) areas of the film are removed during the developed process. After development the resist acts as a mask to etch patterns into the underlying layers, for instance.
The electrical activation of ion-implanted species is carried out by annealing. This causes a redistribution of the impurity atoms which should be kept as low as possible. In order to optimize the electrical behavior of the device, it is important to know how the impurities redistribute during the anneal. The development of appropriate models and simulation programs to predict the diffusion is a major topic in semiconductor technology research.
Main advantages of ion implantation compared to diffusion for the doping of semiconductors are:
is possible.
There are also some disadvantages, such as:
Diffusion of impurity atoms in silicon during processing is important for the electrical characteristics of silicon devices. Various ways of introducing dopants into silicon by diffusion are used and have been studied with the goal of controlling dopant distribution, total dopant concentration, uniformity, and reproducibility.
Diffusion is used to form base, emitter, and collector regions in bipolar device processing, to form source, drain and channel regions, and to dope poly-silicon in MOS processing. Dopant atoms that span a wide range of concentrations can be introduced into silicon in many ways. The most commonly used methods are:
Inhomogeneities of the results of a manufacturing process step caused during the fabrication characterize the manufacturability and yield of a technology. This refers especially to inhomogeneities across the wafer or between different wafers. Processes where these effects are especially important are deposition and plasma etching. Therefore, although topography simulation in fact crosses almost all manufacturing processes mentioned in the previous sections, it is used especially in this work for deposition and etching processes. In addition, as the importance of the three-dimensional effects in shrinking devices and interconnects increases, more accurate methods to track the motion of the interface have to be developed.
Generally, predictive simulation of etching and deposition processes using topography simulators is still limited by lack of knowledge of the physical properties of the material and chemical processes involved. The development of accurate models for reactions paths, the extraction of reliable values for the required parameters and also the development of reduced chemistry models which include only the primary mechanisms needed for practical applications is an important challenge as is reported by ITRS (international technology roadmap for semiconductors)1.1.
There exists a considerable number of commercial and academic tools for topography simulation. They are based on different surface tracking techniques which can be roughly grouped into three different categories. The string-based method, the cell-based method, and finally the level set based method. These different techniques are discussed in Section 2.2 and Section 2.2.3 in detail. This section only introduces the tools based on these techniques and neglects their detailed description.
The string-based techniques have the advantage of a high level of accuracy for moving surfaces, but they need techniques to avoid the formation of non-physical loops and self-intersection of the evolving surfaces. Whereas these disadvantages impact the efficiency of the simulator in two dimensions as can be seen in the ESPRIT [103,60], the three-dimensional implementation of this method is much more expensive in time and memory. Nevertheless, three-dimensional topography simulators based on string techniques such as SPEEDIE [9,10,98,73] exist.
In addition, several implementations based on the cellular method such as an early implementation of the cell-removal algorithm can be found in [29]. The other topography simulator is called MASTER [54]. At our institute Dr. Pyka also implemented a topography simulator based on the cellular method in two and three dimensions for lithography, etching, and deposition processes [64,66].
The third category of methods is the level set method which is, for instance, used by the commercial packages such as SENTARUS1.2. SENTAURUS is an advanced one-, two-, and three-dimensional process simulator for the development and optimization of silicon and compound semiconductor process technologies. After joining ISE to SYNOPSYS their best features have been combined that has led to a great range of capabilities. This new generation of process simulator addresses the important challenges of process technologies. The simulator contains a set of models including calibrated parameters obtained from measurements. Therefore, it enables to simulate a broad range of processes.
Among all techniques, as we will discuss in Chapter 2, the level set method has been known as the best method for tracking the evolution of the surface. Therefore, we have developed and implemented a level set based general purpose topography simulator in two and three dimensions named ELSA (enhanced level set applications). The first version of a two-dimensional topography simulator based on the level set method at our institute was developed and implemented by Dr. Heitzinger. The code was written in Lisp. According to his experiences related to the problems emerging in implementation of two-dimensional topography simulator a second version in two dimensions and a first version in three dimensions capable of handling the more complicated physical models are written. The two- and three-dimensional codes are written in C and C++, respectively.
In Chapter 2 we introduce different well-known techniques used for tracking moving boundaries. These techniques are used in conventional topography simulators.
In Chapter 3 fundamental physical mechanisms of deposition and etching responsible for the creation of both desired and undesired topographic features and a base to understand and model these effects within topography simulation are presented.
In Chapter 4 we describe some physical models for the
deposition of SiO layers from
TEOS in a CVD process. The parameters of these models are
calibrated by comparing simulation
results to SEM images in order to obtain optimal agreement
of measurements and simulation results.
Chapter 5 deals with describing the level set technique and related techniques used for an efficient implementation of our two- and three-dimensional topography simulator.
In Chapter 6 simulation results for the backend of
a 100
CMOS process, where the influence of void formation between metal lines
profoundly impacts the performance of the whole interconnect
stack, are presented. The results from output of our topography simulator serve as input to the subsequent
capacitance extraction.
In Chapter 7 we present the application of the simulator for the simulation of plasma etching processes. The surface kinetics is modeled based on the Langmuir adsorption model. Etching profiles with minimal corner rounding are simulated.
In Chapter 8 the application of the general purpose three-dimensional topography simulator for obtaining the void characteristics in interconnect lines is presented. These characteristics are used to avoid crack formation.
In Chapter 9 we present the application of the simulator to generate structurally aligned grids. The generated grids are used for device simulation with MINIMOS-NT [15].
Finally, Chapter 10 provides an insight into the efficiency and CPU time consumption of three-dimensional topography simulator.