1. Introduction

The aggressive scaling of the fundamental building block of complementary metal-oxide-semiconductor (CMOS) technology, the MOSFET, has not only resulted in the shrinking of device dimensions, but also in the reduction of the gate oxide thickness and the power supply voltage [1]. However, in the 80s the power supply could not scale down at the same rate as the channel length, leading to an increased electric field in the channel. As a result, one of the most important concerns in the field of transistor reliability, the hot carrier (HC) induced degradation has been of high significance [2,3,4,5,6]. Being accelerated by the electric field, the carriers can gain a sufficiently high energy and thus become "hot". These hot carriers impinge on the silicon/silicon dioxide interface and can cause damage via breaking Si-H bonds, thereby generating interface states able to capture carriers and thus become charged. These additional charges introduced into the system are distributed along the channel and perturb the electrostatics of the device resulting, for instance, in a shift of the threshold voltage. Furthermore, they act as additional scattering centers, thereby degrading the mobility and, as a result, the transconductance and linear drain current. This phenomenon is called hot-carrier degradation. It has been known for more than four decades and numerous modeling attempts have been undertaken. However, the exact location of the defects, as well as their temporal buildup during stress, is rarely studied. Moreover, although a considerable number of HCD models have been proposed, most of them are empirical/phenomenological and only a limited number of physics-based models exists.

I. Starkov: Comprehensive Physical Modeling of Hot-Carrier Induced Degradation