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To reveal and understand the physical picture behind HCD, it is essential to obtain quantitative information regarding the spatial distribution of hot-carrier induced interface states and oxide trapped charges [108]. For this purpose, the charge-pumping technique proves to be a promising approach. However, among numerous variations of the basic CP technique [173], to obtain the Nit and Not lateral profiles the measurement method with varying amplitude (high/low-level) of the gate pulse is employed [66,178,179,177]. In addition to the interface state generation the bulk oxide charge build-up is an important component often linked with the hot-carrier stress in literature, which is of special significant in high-voltage devices. Thus, in this Section a careful study of the most widely used extraction techniques of spatial trap distributions from CP data is presented, highlighting their limits of validity and linking them with the developed HCD model.
As in the previous Section 4.2, for these investigations a 5V n-type MOSFET fabricated on a standard 0.35um CMOS process (Figure 3.2) is used. The lateral coordinate x refers to an origin placed at the left edge of the source contact. A device channel width of W = 10um was chosen to obtain a sufficient charge pumping signal. As reported in Section 3.3, since we are dealing with a long-channel device (gate length Lg = 0.5um) the WCC of HCD are reached atVgs = 0.4Vds. Therefore, the device was stressed at Vds = 6.5V, Vgs = 2.6V and a temperature of T = 40oC for 105s.
An experimental scheme was employed whereby the gate of the transistor is connected to a pulse generator, while source, drain and substrate contacts are grounded. As it was suggested in [177,175], the CP current at the drain (Icp,d), source (Icp,s) and substrate (Icp,sub) are measured. Due to the presence of the damage dose provided by the multiple-carrier component of the Si-H bond dissociation process (explained in Section 3.1) it is important to perform separate current measurements. To be more precise, the assumption used in [178,179] that the damage is induced only near the drain edge of the gate contact is incorrect. As a consequence, the drain component of the CP current can not be defined as
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(4.10) |
The gate of the MOSFET was pulsed by a trapezoidal waveform at a frequency of f = 100kHz. A Vgl = -5V was used, while Vgh was increased from -4 to 3V (varying high-level technique) and Vgh was set at 4V, while Vgl was decreased from 3 to -5V (varying low-level technique) in 0.02V increments. Here, Vgl and Vgh are the low and the high levels of the gate pulse, respectively (see Figure 4.10). Such a small voltage step is required in order to obtain a sufficient spatial resolution.
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in the case of varying low-level CP technique. Here Vth(x) andVfb(x) are the local threshold and flatband voltages described in Section 4.1. If the influence of the interplay between oxide and interface charges is small enough, Vth(x) and Vth(x) keep the initial form corresponding to an undamaged device during hot-carrier stress. Otherwise necessary corrections of Vth(x) and Vth(x) after each stress time step must be performed [178,177,66]
where ΔNit and ΔNot are the changes between pre- and post-stress concentrations of interface traps and bulk oxide charges, respectively, Cox is a parameter used to depict the oxide capacitance per unit area and will be described below. The coefficient 2 in the denominator of the last term in (4.13) is noteworthy. The interface states are assumed to obey a homogeneous distribution over energy in the band-gap [183,66]. Also, traps situated above mid-gap assumed to be acceptor-like while those in the lower half of the band-gap are donor-like. In the case of an n-MOSFET with a positive bias applied to the gate, the net charge is negative. The reason behind this is the charging of the acceptor-like interface states. Not disposing at the real distribution of traps over energy it is suggested that the charge stored in these states is Qit = -qNit(q)/2, thereby considering a uniform distribution.
In the case of the absence of a significant amount of oxide charges generated under hot-carrier stress it is possible to use a simplified method for Nit extraction and consider only the effect of Nit on the calculated Vth. Namely, only varying high-level or varying low-level CP technique can be used [174].
All approaches described below have been developed in order to obtain the spatial distribution of both types of defects (Not(x) and Nit(x)) induced by HCD. There are four main concepts for the characterization of the interface states and oxide-trapped charges in MOSFETs: Lee's [178], Li's [179], Chim's [177] and Mahapatra's [66]. Furthermore, the key issues of these extraction procedures are emphasized.
The aforementioned extraction techniques assume that each value of the transistor's local threshold and flatband voltage corresponds to only one position of the coordinate x before and after stress. That is, the effect of the trapped charges on the Vth(x) and Vfb(x) distributions is one dimensional - the shift of the local threshold and flatband voltages at channel position x can be induced only by the charges at position x. This assumption can be additionally examined by using a modified charge-pumping technique where both the high level Vgh and the low level Vgl of the applied gate pulse are alternating during measurements [175,177]. However, an investigation of the modified CP experimental schemes for verification of this assumption is out of the scope of this work.
