List of Figures

• 2.1. Box $i$ with six neighbors
• 2.2. Splitting of interface points: Interface points as given in a) are split into three different points having the same geometrical coordinates b)
• 2.3. The complete equations are a combination of the boundary and the segment system. This combination is controlled by the transformation matrix and depends on the interface type. In the upper figure, the case for Dirichlet boundary conditions including substitute equations is shown, in the lower figure for all other cases.
• 2.4. Comparison of transient and frequency-domain-based approaches [233]. The dashed rectangles of the $\textrm {S}^3\textrm {A}$ approach symbolize complex-valued equation systems, the other real-valued ones.
• 2.5. These figures [160] show a standard $\Pi$-type small-signal equivalent circuit of a HEMT (left) and a T-type eight-element small-signal equivalent circuit of an HBT. The dashed rectangles denote the intrinsic devices, the terminal resistances can be additionally included in the simulation.
• 2.6. Comparison of small-signal and large-signal simulations. In the case of too high RF power, harmonics are generated within the non-linear devices. These additional voltage and current vectors cannot be taken into account by linearized small-signal approximations [45].
• 3.1. Voltages and currents of a two-port device/network.
• 3.2. Traveling waves at a two-port device/network.
• 3.3. Definition of S-parameters.
• 3.4. Complete $f_\textrm {T}$ curve of a bipolar junction transistor (left). Slope of the absolute value of the short circuit current gain and the cut-off frequency at the unity gain point at $\ensuremath{I_\mathrm{C}}= 0.865\,$mA (right).
• 3.5. Overview of the MINIMOS-NT small-signal capabilities.
• 3.6. Simple diode structure under investigation. The boron concentration in the p-doped half on the left is $1\times 10^{17}\ {\textrm {cm}}^{-3}$ equal to the phosphorus concentration in the n-doped part of the diode.
• 3.7. The left figure shows the results of the transient simulations for the three amplitudes $A = 10\$mV, $A = 250\$mV, and $A = 1\$V. The small figures depict the results of the Fast Fourier Transformation of the respective cathode currents.
• 3.8. The upper left figure compares the small-signal results of MINIMOS-NT and DESSIS. The other three figures compare the small-signal results of MINIMOS-NT with its transient results: In the upper right figure the capacitance versus the frequency is shown. The argument versus the frequency is given in the lower left figure. In both figures, different number of periods (P) and number of steps per period (S) are compared. Finally, the dependence of the relative errors and the time scaled to the small-signal result (time ratio) on the number of transient steps is illustrated in the lower right figure. The number of periods is $2$, the frequency is 1$\,$MHz and the transient data is compared with the small-signal results. The trade-off between the reduction of the relative errors and the increasing computational effort can be clearly seen.
• 3.9. These figures analyze the effort for the extraction of $f_\textrm {T}$ by conditional stepping. On the left side, two different sets of lower and upper boundaries are compared for an error value of $10^{-3}$. Whereas for the wide boundaries of 10$\,$GHz and 100$\,$GHz 24 steps are required, the narrow boundaries of 30$\,$GHz and 40$\,$GHz reduce this effort down to five steps. On the right side, the number of steps depending on the narrowness of the boundaries for different errors are shown.
• 3.10. In the left figure, the three transport models are compared with quasi-static simulation results of MINIMOS-NT as well as with Monte Carlo data. The right figure shows the cut-off frequency depending on the gate voltage. Whereas for larger devices, the difference is again minimal, the superiority of the six moments transport model for smaller devices can be clearly seen.
• 3.11. Part of the investigated device structure with a depth of 1$\ \mu$m.
• 3.12. Gate drain capacitance versus gate voltage at $V_{\textrm {D}} = 0\ V$: comparison of simulation results of MINIMOS-NT and DESSIS.
• 3.13. Two-Port parasitic equivalent circuit.
• 3.14. Results of mixed-mode AC simulations with compact models only: the resonant circuit on the left side and the band rejection filter on the right side.
• 4.1. All equations marked for pre-elimination (*) are moved to the outer system matrix, the others remain in the inner one [65,228].
• 4.2. On the left the completely compiled system matrix of a discretized two-dimensional MOS transistor structure assembled by MINIMOS-NT is shown. The magnitude of the entries are encoded by the colors according to the legend in the right. Some regions with problematic equations are indicated by red dashed rectangles. After the pre-elimination, the inner system matrix (right) does not contain the problematic equations any more. The dimension is not significantly reduced since the majority of equations is not affected.
• 4.3. In comparison to the pre-eliminated structure, the reordering algorithm significantly reduces the bandwidth from 2,867 to 102 in order to reduce the factorization fill-in (left). The circle indicates the range of the cut-out of the scaled matrix shown in the right figure. The scaled inner system matrix has diagonal entries equal unity, which is demonstrated by the red color. Since only the values are changed, no structural difference can be seen in comparison to the sorted matrix.
• 4.4. Schematic assembly overview.
• 4.5. Former (left), refined (center), and final (right) administrative scheme.
• 4.6. Transformations involved if three segments share one physical grid point.
• 4.7. Graphical representation of the multiple transfer problem.
• 4.8. Comparison of the one-phase (upper) and four-phases (lower) approach. In the latter case the implementation of the simulator is much more complicated as the assembly module requires a specific assembling sequence. Whereas in the one-phase approach the loop over all models is processed only once, it has to be processed four times in the four-phases approach. In addition it is necessary to call specific preparation functions and each model implementation has to take the current phase into account, which leads to complicated codes.
• 5.1. Schematic overview of the linear modules [230].
• 5.2. The hierarchical concept [65,228].
• 5.3. Concept of single- (left) and multi-threaded (right) stepping algorithm. Whereas the former calculates all 55 steps subsequently, the latter uses five processes to calculates eleven steps each.
• 5.4. Comparison of a canonical shared memory (left) and message passing non-shared memory (right) architectures [34].
• 5.5. User time, number of operations (left), and memory consumption ratios (right) depending on the GMRES(M) restart factor $m$ for the two-dimensional (above), three-dimensional (center), and mixed-mode simulations (below).
• 5.6. Solving times (average, minimum, maximum) on the Intel computer. All times are scaled to the in-house ILU-BICGSTAB in the center.
• 5.7. In the left figure, the relative PARDISO real/wall clock times (average, minimum, maximum) versus the number of processors/threads on the IBM cluster. The user time in the right figure increases due to the parallelization overhead.
• 5.8. Scaled results for the six moments transport models (upper figure). The lower figures show scaled results for the energy-transport (left) and the drift-diffusion (right) transport models.
• 6.1. Simulated device structure together with pad parasitics used for S-parameter calculation [161].
• 6.2. Comparison of simulated and measured AC collector current i $_\textrm {C}$ over AC input power $P_\textrm {IN}$ (left). Comparison of simulated and measured AC output power $P_\mathrm{OUT}$ over AC input power $P_\textrm {IN}$ (right).
• 6.3. S-parameters in a combined Smith/polar chart with a radius of one from $50\$MHz to $10\$GHz at $\ensuremath{V_\mathrm{CE}}= 3\$V, ${\ensuremath{J_\mathrm{C}}} = 2\,$kA/cm$^2$ (upper left), ${\ensuremath{J_\mathrm{C}}} = 8\,$kA/cm$^2$ (upper right), and ${\ensuremath{J_\mathrm{C}}} = 15\,$kA/cm$^2$ (lower left). In the lower right figure the short-circuit current gain and matched gain versus frequency at ${\ensuremath{J_\mathrm{C}}} = 15\,$kA/cm$^2$ is shown.
• 6.4. Active antimony concentration of the investigated SiGe Heterojunction Bipolar Transistor (large device).
• 6.5. Comparison of simulated and measured forward Gummel plots at $V_\textrm {CE}= 1\$V.
• 6.6. The figures compare S-parameters in a combined Smith/polar chart with a radius of one from $50\$MHz to $31\$GHz at $\ensuremath{V_\mathrm{CE}}= 1\$V for ${\ensuremath{J_\mathrm{C}}} = 28\,$kA/cm$^2$ (left) and ${\ensuremath{J_\mathrm{C}}} = 76\,$kA/cm$^2$ (right) for a large device structure and a small one embedded in a circuit.
• 6.7. The cut-off frequency $f_\textrm {T}$ versus collector current $I_\mathrm{C}$ at ${V_\textrm {CE}} = 1\$V (left) and the short-circuit current gain versus frequency (right) is depicted [233].
• 6.8. On the left, the cross section of a MESFET in SiC is shown and on the right a comparison of measured and simulated DC IV characteristics [12].
• 6.9. Comparison of measured and simulated S-parameters in a combined Smith/polar chart with a radius of one (left). Small-signal current and power gain (right) [12].
• 6.10. The three subcircuits which are used in the example circuits are shown on the left side. They are parts of the three circuits depicted on the right [231].
• 6.11. Result of transient simulation of the amplifier circuit with $V_\textrm {ac}=10\$mV and $f = 2.4\$GHz [231].
• 6.12. Results of small-signal simulations of the resonant circuit: absolute value (left) and argument (right). The results are compared with ADS simulations using a VBIC95 model of a similar transistor [231].
• 6.13. Result of the transient simulation of the oscillator: output $V_\textrm {pin2}$ in the initial phase (left) and in the state of equilibrium (right) [231].
• 6.14. Structure of the simulated double-gate MOSFET devices. The gate length is varied from 250$\$nm down to 25$\$nm [83].
• 6.15. These four figures show the increasing errors of the macroscopic transport models with decreasing gate lengths. Whereas at $L_\textrm {g}=$250$\$nm in the upper left figure the difference of the drain currents is minimal, it can be clearly seen that for $L_\textrm {g}= 50\$nm the six moments transport model delivers the best results. However, for extremely small gate length, it loses its advantages and even more moments would be necessary. Note that the drift-diffusion model results in terminal quantities which underestimates the Monte Carlo results.
• 6.16. These four figures show the cut-off frequency versus the drain current and the much higher sensitivity of that small-signal figure of merit is demonstrated.
• C.1. SEILIB class diagram.
• C.2. Class diagram of the MINIMOS-NT test system based on the SEILIB library.
• C.3. Class diagram of the SEILIB optimization system.