Electromigration can trigger system failure at an undefined point in future and is the main reliability issue in modern integrated circuits. The phenomenon is particularly likely to afflict the thin, tightly spaced interconnect lines of deep-submicron designs. Since its importance to microelectronics back-end technology was initially recognized, engineers, physicists, and material scientists have tried to understand and model electromigration. The necessity to reduce the risk of electromigration has always been tremendous and with the introduction of new technologies it has been increasing steadily. Because the phenomenon does not manifest itself until a circuit has been in operation for months or even years, electromigration cannot be prevented during the course of product testing.
An ultimate hope of integrated circuit designers today is to develop a computer program which predicts the behavior of thin film metalizations under any imaginable condition. Contemporary integrated circuits are often designed according to simple and conservative rules to ensure that the resulting circuits meet reliability goals. This precaution leads to reduced performance for a given circuit and metalization technology. Compared with previous work, our approach reveals an improvement in two mayor points. First, the classical multi-driving force continuum model is extended by models which describe the influence of mechanical stress on microstructural properties of metal and second, a newly developed, finite-element-based scheme enables an efficient numerical solution of the three-dimensional formulation of the problem, while the physical soundness is preserved. A satisfying assessment of electromigration reliability can only be achieved through a combination of experimental methods and the utilization of Technical Computer Aided Design (TCAD) tools. Therefore, we also discuss possible usage scenarios of TCAD tools in connection with the results of accelerated interconnect tests. The TCAD analysis of the electromigration reliability of interconnect structures has to be carried out on at least two levels. The first level is without any doubt a physical one, that means application of the most complete and comprehensive models to interconnect portions of moderate size. The second level of analysis combines the results of the first level in order to assess the electromigration reliability of an entire chip.