Continuing the downscaling of transistor feature size is the key to the tremendous success of CMOS technology. The scalability allows the integration of more transistors per unit area, while increasing transistor performance and reducing costs per operation. An anticipated performance enhancement was achieved at the expense of an increase in subthreshold and gate leakage currents. Keeping power dissipation due to leakage currents under control forced device engineers to look for new technological solutions in order to deliver the projected performance gain. At the 90 nm technology node, stress technique was introduced to enhance performance while keeping the MOSFET design intact. Since then, stress-induced mobility engineering has become a key technique for increasing the performance of modern CMOS devices.
A shear distortion in the Si crystal lattice inherent to [110] uniaxial stress induces, apart from the nonlinear valley shift, a more pronounced modification in the conduction band. Shear strain substantially changes both the longitudinal and the transversal effective masses in the out-of-plane valley minima. The decrease of the mass in the transport direction along tensile [110] stress and the valley re-population which results from the valley shifts lead to mobility enhancement. Effective mass variation is even more pronounced in the ultra-thin silicon films of the silicon-on-insulator transistor, as illustrated in Fig.1.
Double-gate silicon-on-insulator transistors with ultra-thin Si bodies are good candidates for the far-end ITRS roadmap scaling. A superior electrostatic channel control helps reduce the leakage current and allows scaling the channel length down to 5 nm, while maintaining reasonable subthreshold slope, satisfactory Drain Induced Barrier Lowering (DIBL), and an acceptable gain. Due to size quantization in thin Si films the energy spectrum of each valley is split into a set of two-dimensional subbands. In transport simulations, inter-subband scattering becomes important, especially in ultra-thin body field-effect transistors at high effective fields, where degeneracy effects due to Fermi statistics become important. Although the Fermi blocking factor is canceled out by the scattering integral for elastic processes, it cannot be ignored in inelastic scattering, even when it is small. Accurate inclusion in simulation scheme of the degeneracy effects due to the Pauli exclusion principle, is essential for a correct treatment of scattering and is crucial for mobility calculations. Accurate transport modeling in modern field-effect transistors for arbitrary substrate orientations and general stress conditions becomes the important issue and prompts the development of new, more efficient simulation algorithms. Results of mobility calculations in a strained double-gate MOSFET as a result of the solution of the multi-subband Boltzmann equation by means of a Monte-Carlo method are illustrated in Fig. 2.
Scaling the MOSFETs below the 45 nm technology node makes the theoretical description and modeling of carrier transport in these devices even more challenging. When device size becomes shorter than the phase coherence length, complete information about carrier dynamics inside the device including the phase of the wave function is needed and one has to resort to a full quantum-mechanical description including scattering. The development of numerical methods for dissipative quantum transport is an urgent issue. The Wigner function method is attractive because it includes all scattering mechanisms naturally via the scattering integrals, allowing the development of a transport model which accounts for both quantum interference phenomena and realistic scattering mechanisms.