Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

6.2 Capacitance-Voltage Measurements

Not only measuring of , but also measuring the gate capacitance allows the extraction of defect related parameters. First a reference CV curve is measured and then the device is stressed under well defined conditions. Afterwards, a second CV curve is recorded and from the variation between the pre- and post-stress CV curves one can extract various defect properties. However, in this work, CV curves have not been used for defect characterization, but are important for the calibration of the electrostatics of our reliability simulator Comphy, which will be introduced detailed in Section 4.

For recording a CV curve a DC-voltage  is applied at the gate of the device under test (DUT) which is superposed with small AC signal, which typically has a frequency between 10 kHz and 1 MHz. The mean voltage  is then swept from accumulation to inversion. By measuring the gate current at every -step, the capacitance can be computed by

with f being the used frequency, being the amplitude of the AC-signal and  being the measured gate current. Depending on the defect properties and the charge trapping kinetics, the shape of the CV curves can change which makes CV measurements a powerful tool for reliability characterization which provides valuable information about the energetic position of the traps [222, 140].

The CV curves in Fig. 6.8 were recorded on Tech. B employing a Keithley 590 CV analyzer using a frequency of and are plotted normalized by . The temperature has been swept from 4 K to 300 K. As can be seen for both nMOS and pMOS, the transition between depletion and inversion becomes sharper towards cryogenic temperatures. This is because the Fermi distribution becomes sharper and thus scans a smaller energy region. Figure taken from [MJC4].