Transistors used in digital applications should be able to switch between ON-state and OFF-state as quickly as possible. At cryogenic temperatures, the switching between ON- and OFF-state is superior compared to room-temperature, because of the increased ON-state current and the increased transconductance. However, at scaled devices resonance phenomena have been observed across various technologies including 40 nm bulk [223], 28 nm bulk CMOS [200, 224], 40 nm SOI [225], 22 nm FDSOI [226] and 16 nm FinFET [227], which can lead to large humps in the transition from the OFF- to ON-state. Such humps have been measured on Tech. A on nMOS SmartArray A (Fig. 6.9 (left)) with dimensions at 4.2 K with [MJC5] and on a device of the nMOS-flavored SmartArray B in Fig. 6.9 (right) with dimensions at 4.2 K with .
These humps in the () curves can be extremely prominent and can even lead to a negative transconductance , as can be seen in Fig. 6.10.
The resonances are caused by quantum confinement in the channel due to ionized dopants, impurities or defects. Resonant tunneling leads then to the occurring resonance in . In literature, this is often referred to as Coulomb oscillation [227, 224, 223]. The resonance shows a large and temperature dependence. A larger leads to a fade out of the resonance, as can be seen in Fig. 6.9 (left). This is caused by the drain-induced barrier lowering (DIBL) effect which allows more carriers to overcome the barrier and diminishes the reduced conductance caused by the resonance [227]. Towards higher temperature the resonance fades out, because the higher thermal energy allows more carriers to overcome the occurring tunneling barriers [227].