Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

Part I Modeling and Simulation of Defects

2 Defect Candidates

Reliability issues such as BTI, HCD, or charge noise, i.e. RTN, are caused by electrically active defects that can be located in the oxide or at its interface to the semiconductor bulk. These defects are introduced in the device during manufacturing, even in very optimized processes, or can be created during device operation at nominal bias conditions and temperatures and their formation can not be avoided. Since these defects typically have a negative impact on the device performance or, in the worst case, can even lead to the failure of the device, it is of major importance to understand how defects emerge and how they influence the device performance. Over the years, the manufacturing processes have considerably improved and as a consequence the number of active defects could be significantly reduced. Still, there are many applications which rely on an extremely low noise level and very narrow reliable operation conditions which is further motivation to investigate the physical processes involved in charge trapping. Since defects occur in a large variety, many different approaches are used for examinations, from theoretical tools such as DFT or TCAD, electrical examination tools as presented in Part II of this work, or physical characterization methods such as electron paramagnetic resonance (EPR) spectroscopy, X-ray photoelectron spectroscopy (XPS), or secondary ion mass spectroscopy (SIMS).

The combination of all these tools allows to search for specific defect candidates, which may play a major role in the device degradation during operation. The trapping properties of suitable defect candidates, such as relaxation energies, defect densities, trap level, and spatial position can be theoretically studied and linked to various experimental approaches using reliability simulations as presented in Chapter 4. The most important defect candidates for electrical reliability studies are introduced in the following sections.

2.1 Interface Defects

Silicon dioxide is the most common insulator in MOSFET technologies. During the fabrication of devices, SiO2  grows natively on silicon wavers when exposed to air via oxidation, which makes it an ideal candidate as an insulator. The resulting thin layer (with a thickness below 1 nm) is called native SiO2 . Alternatively, nitrited SiO2  (SiON) is used as insulator to decrease the gate leakage current and to prevent dopants from diffusing from the channel into the insulator. The defect behavior in SiON insulators is similar to the one in pure SiO2  , which typically allows using the simplified SiO2  system in simulations [136].

The lattice mismatch between the amorphous structure of the insulator layer and the semiconductor makes the presence of a certain amount of defects close to the interface inevitable. The interface defect density strongly depends on the combination of the materials used for the semiconductor and insulator and the processing conditions. Note that for Si/SiO2  systems densities on the order 10¹⁰ cm⁻²eV⁻¹ can be achieved [137]. For this material system, the best understood interface defect is the Pb  center, which can appear on both, the (111) and the (100) oriented surface [138, 139]. In general, the Pb  centers have been observed to occur in different chemical variations: The P center of the form (SiSi) and the P center, whose atomistic structure is not completely understood yet, are depicted in Fig. 2.1. Due to the unpaired electron at the Si side, the defects are also called dangling bonds.

There are at least two trapbands corresponding to the Pb  centers, one above and one below Si midgap, which allow electron capture and emission from and to the channel, respectively [141]. The trap levels of such interface defects lie within these trap bands, and they typically have small relaxation energies which leads to small relaxation times compared to bulk oxide defects [142]. Thus, the different relaxation energies can be used as an indicator which defects might be responsible for measured signals, as done e.g. in Section 7.4.

The oxidation of amorphous SiO2  on the Si substrate leads not only to interface defects but also to a continuous change in the density of states and the corresponding band edges [136], as shown in Fig. 2.2. This behavior can be explained by a gradual change in the ratio of silicon and oxygen atoms between bulk SiO2  and the Si substrate. The gradual change in the density of states and linear band edge structure has to be be considered in device simulations, e.g. by correcting the WKB tunneling factors [136]. Fig. 2.2 shows the transition layer from amorphous bulk SiO2  to the Si substrate which shows a thickness of 0.3 nm to 0.4 nm. This has the consequence that in high-κ devices, which typically have a very thin SiO2  layer of below 1 nm between the substrate and the high-κ material, no bulk SiO2  occurs.