The generation of a set of design-space sample points by process and
device simulation experiments forms the basis for further analysis.
As described in Section 2.1, various TCAD tasks
aim at characterizing a VLSI process in terms of
statistical behavior and sensitivity to uncertain control parameter
values as well as at tuning its performance to specifications derived
from chip design and management. Furthermore, TCAD creates a number
of tasks on its own dealing with the calibration of simulation tools
and the generation of response surface models, to name a few.
To liberate the
TCAD engineer from defining and performing these tasks
manually
,
automation and programming support on the task level are
a major concern for a TCAD environment. VISTA/SFC offers
evaluable entity (EVE) objects that establish an object-oriented
approach to many task-level tasks; they shall be addressed in more
depth in Chapter 8.