Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs

1.2 Reliability of MOSFETs

As outlined in the previous section, the introduction of the forming gas anneal has established a process step to enable the passivation of the majority of interface defects between bulk Si and amorphous SiO₂ (a-SiO₂), allowing the fabrication of highly stable MOSFETs. However, with the continuous down-scaling of CMOS transistors to a few nanometer channel length and only a small number of atomic layers thin gate dielectrics, the impact of charges captured at single electrically active defects located in the vicinity of the channel has become more pronounced. Due to the perturbation of the electrostatics upon charge capture, a single defect can eventually lead to failure of a MOSFET. The device parameter alteration effects due to these charge trapping events are summarised under the term Bias Temperature Instability (BTI). Next to BTI, enhanced electric field strengths in the lateral channel direction from the source to drain contact can lead to breakage of previously passivated dangling bonds. This bond breakage is a result of carriers with high kinetic energies scattering at the interface region, thereby creating defect states which then can capture and emit charge. Thus, the mechanism is referred to so called Hot Carrier Degradation (HCD). Also, the effect of carriers tunneling through the insulating layer via hopping at pre-existing oxide defects, termed Trap-Assisted Tunneling (TAT) leads to enhanced leakage current resulting in additional power losses. Furthermore, as a consequence of TAT, defects within the bulk oxide can be created or high energetic carriers multiply due to impact ionization at large stress oxide field strengths. These additional leakage current following from these events are referred to as Stress Induced Leakage Current (SILC) and eventually lead to oxide breakdown. This failure mechanism is typically characterized by Time-Dependent Dielectric Breakdown (TDDB) experiments. In the following, the role of BTI, gate leakage currents and HCD on the reliability of MOSFETs will be briefly outlined and the state of the art of research on these topics will be discussed.

1.2.1 Bias Temperature Instabilities

The alteration of the characteristic parameters of a MOSFET, e.g. flat band voltage V_fb, threshold voltage V_th, carrier mobility and sub-threshold slope , is known to be accelerated by enhanced temperature and gate bias stress. Therefore, these deviation phenomena have been collected under the term Bias Temperature Instability (BTI) [54]. BTI has been first described in the late 1960s by Miura et. al [55]. The stabilization of silicon surfaces [56] was the main research focus at that time, and the first BTI characterization attempts have been related to the mechanisms of ion impurity diffusion and thermally assisted tunneling [57, 58]. The main features observed were the power-law like development of the shifts of the threshold voltage based on empirical parameters, i.e. a time exponent of about 0.2, thermal activation with activation energies up to 0.2 eV and voltage acceleration with exponents in the range of 2 to 3 [59, 60]. Based on these observations, an expression for ∆V_th was given by [59]

with a constant prefactor and the activation energy as fitting parameters. This method is easy to apply and is therefore still widely used, however, it fails to connect the degradation with the underlying physical mechanisms and additionally implies an infinite degradation trend because no saturation of the ∆V_th is considered. Moreover, the expression was derived from observations of negative BTI (NBTI) in Si-based pMOSFETs and cannot be generally applied to positive BTI (PBTI) or BTI observations on different technologies. For example, if more than one dominating trapping mechanism is prevalent, different slopes for the time evolution of ∆V_th may be observed which cannot be captured by this simple model. Therefore, in the past decades more sophisticated models have been developed to describe the underlying physical mechanisms more accurately. Heiman et. al connected threshold voltage shifts in Metal Oxide Semiconductor Capacitor (MOSCAP)s to charge trapped in the oxide [61], applying a Shockley and Read like kinetic statistics [62]. This modeling approach, however, only considers elastic tunneling of charge carriers from the channel to the defect. From the 1970s on, also reaction and diffusion limited regimes of the NBTI degradation were frequently proposed to originate the effect [63, 64]. In the latest version of this model, interface defect creation at high oxide field strengths has been proposed. This stems from hydrogen that is released causing additional dangling bonds at the interface (reaction), followed by hydrogen diffusion and accumulation in the oxide (diffusion) [65].

A different approach to a reaction-diffusion model was presented by Kirton and Uren, who first connected single defect charge transitions to 1/f noise and RTN signals in the context of the Non-Radiative Multi-Phonon (NMP) framework [66, 67]. Tewksbury later first modeled threshold voltage shifts in MOSFETs applying the NMP theory to charge transitions involving oxide defects [68, 69]. Both, RTN and V_th shifts are therein explained by an inelastic tunneling process at pre-existing oxide defects. It took more than another decade until Grasser’s two stage model [70] was the first attempt to model both, a recoverable and a permanent component of BTI as observed in Si/SiO₂ systems. The recoverable part (stage 1) is explained by the formation of E′ -centers from oxygen vacancies which can be charged and discharged. The permanent part (stage 2) is described with a 3-state model and caused by the de-passivation of P_b,0-centers triggered by charged E′ -centers.

Further experimental observations on charge capture and emission events of single defects in small area devices such as Time-Dependent Defect Spectroscopy (TDDS) [71] studies and Random Telegraph Noise (RTN) [72] measurements initiated the refinement towards a four-state defect model for the recoverable component, which is able to explain both single charge transfer events in small area and the superposition of such in a defect ensemble in large area devices [73, 74]. This extension allowed for the description of phenomena like fixed/switching traps [75], and anomalous, temporary and reversal RTN [76]. The explanation of such details in RTN, i.e. charge trapping kinetics at a single defect, requires the existence of meta-stable defect states, which has been shown to be consistent with ab-initio studies for a number of suspected defect candidates [77]. Therefore, besides charge trapping is still not accepted as the unique mechanism causing BTI [78], the NMP model has provided deep physical insight into charge trapping as the origin of BTI.

BTI on SiC power MOSFETs has been characterized early after the development of wide-bandgap devices, with a focus on the time-dependence after bias-stress [79, 80] and its temperature dependence [81]. These works mainly extracted after bias stress as a function of the stress time by evaluating the based on post stress ID (VG ) measurements, thereby acknowledging the strong read-out time dependence of after a stress phase within in their measurements. Later Okayama et. al [82] discovered an accelerated recovery when negative bias stress is applied after a positive stress phase. This mechanism can be explained by reduced emission times of previously trapped electrons during the negative bias phase. Reduced ∆V_th was also observed at elevated , speculating that this effect evolves from ion diffusion [81], thereby neglecting the possibility of accelerated recovery at higher  [83]. The role of nitrogen passivation in NO containing ambient leading to an improved interface stability, i.e. less electron charge trapping, has been also studied [84] and the first structural defect candidates, i.e. interface states with more than 0.6 eV below the SiC conduction band together with nitrogen related defects and oxygen vacancies, have been proposed [85]. Switching bias stress experiments for equal positive and negative bias revealed negative shifts and therefore higher stability of trapped holes compared to a unipolar bias stress [86]. While comparisons between BTI in Si and SiC MOSFET are drawn frequently and might be valid due to the same nature of oxide defects [CSC8, CSC5], it was also emphasized that the interpretation of BTI measurements with state-of-the-art characterization methods developed for Si MOSFETs can be misleading [87, 88, CSJ10] when applied to SiC MOSFETs due to the wide distribution of the defect capture and emission time constants. Puschkarsky et. al conducted detailed BTI experiments under AC and DC gate bias stress, revealing accelerated temperature recovery [89] leading to seemingly less degradation at increased . Furthermore, an accurate model to reproduce the extracted charge trapping kinetics with activation energy maps has been demonstrated [90, 83]. Additionally, recently a frequency independent switching cycle dependence of ∆V_th at bipolar gate bias operation in trench MOSFETs has been reported [91, 92, 93], however, not been explained by a physical mechanism. Note that a similar effect has been noticed in Si-based MOS devices employing SiO₂ as an insulator before and has been explained by the gate-sided hydrogen release model [94, 95].

Besides the detailed experimental studies conducted to characterize BTI in SiC MOSFETs for more than a decade, a physical defect-centric modeling approach to consistently describe the charge trapping mechanisms at the device level has not been presented so far. This gap from experimental observation to device modeling with defect bands that can be compared to parameters obtained by ab-initio methods from defect candidates is aimed to be narrowed down within this thesis [CSC8, CSJ6, CSC1].

1.2.2 Gate Leakage Currents and Oxide Breakdown

The charge blocking capability under electric fields of an ideal insulator within a MOSFET is intrinsically limited by its band offsets, i.e. the energetic barriers defined by the conduction and valence band edges of the substrate to those of the insulator, as well as the thickness of the dielectric layer. With ongoing scaling of insulators in CMOS technology Fowler Nordheim (FN) and direct tunneling (DT) currents, a result of charge carriers being able to tunnel through the energetic barrier given by the insulator, lead to detrimental on- and off-state losses. This intrinsic limitation can further be decreased by the presence of charge traps in real devices. Next to the capture of charge in the oxide and the resulting perturbation of the electrostatics across the MOS structure (c.f. BTI), defects in the insulator can also act as charge transition centers between the channel and the gate electrode. This so-called Trap-Assisted Tunneling (TAT) emerges from the same inelastic charge tunneling mechanism as in the case of BTI as will be outlined in the following.

Conduction via defects within the band gap of a semiconductor material acting as transition or recombination centers have been early studied and described by Mott [96]. The modeling efforts have later been extended by Miller and Abrahams to describe charge hopping in doped crystalline semiconductors [97]. While these early modeling approaches considered purely elastic tunneling processes, Schenk et. al developed a model for defect with deep trap levels to band transitions accompanied by a multi-phonon relaxation [98], which was later extended by Herrmann et. al to model leakage currents through MOSFETs used for memory applications [99]. This model represents to date the core of most TAT modeling approaches based on NMP theory [100, 101, 102, 103]. Later, the TAT model of Schenk et. al has been further refined and extended to model thermally activated leakage currents through high- dielectrics used in MOSFETs by the group of Larcher [104, 105, 106, 107]. It should also be noted that a full quantum mechanical description of TAT currents within the NMP theory, as presented e.g. in [108, 109, 110], is most rigorous and necessary at for instance cryogenic temperatures [111]. However, its application on a device level simulation is often prohibitively expensive due to its large computational cost and often not necessary within the typical device operating temperature range, as will be discussed in Chapter 4.

In SiC MOS structures, thermally activated gate leakage currents below the FN regime have been observed recently [112, 113, 114] and were suspected to be trap-assisted with further conduction to the insulator conduction band [115, 116]. Thereby, a “sweet spot" of a defect band in spatial and energetic dimension enables this current conduction via traps. A close investigation of this hypothesis by physical modeling of these charge transitions will be presented within this thesis.

Increased FN, DT, and TAT currents at high stress oxide fields can further lead to defect creation by high energetic carriers, e.g. impact ionization [117] within the oxide. The resulting increased defect density following the oxide field stress further exaggerates gate leakage currents, hence termed Stress Induced Leakage Current (SILC) [118, 119]. It was already discovered in the 1980s that the resulting current was caused by thermally assisted tunneling from the channel to newly created defects [120, 121, 122]. Thereafter, the ongoing oxide degeneration eventually leads to a breakdown of the insulating capability by forming permanently conducting filaments, which is typically characterized by transient current measurements at increased bias and temperature stress within the TDDB method. Already in 1973, defect creation was suggested to be the responsible mechanism for TDDB, with a distinct oxide thickness dependence, predicting a stronger impact for thinner oxides [123]. While modeling attempts have focused on impact ionization for both SILC and TDDB [124, 125], the structural reconfiguration of defects could also explain the formation of leakage paths in the oxide and was able to explain correlation of single steps in gate tunneling currents and drain currents [126].

1.2.3 Hot Carrier Degradation

Contrary to BTI, the more permanent device parameter ( , , ) alteration due to HCD is attributed to defect creation at the Si/SiO₂ interface in Si-based MOSFETs. While the effects of BTI are extracted at high gate and low drain bias, which leads to a uniform oxide field distribution and low energetic carriers across the lateral MOSFET channel coordinate, HCD is typically characterized at the high drain bias and low gate bias regime, as shown in Figure 1.6. In this regime highly energetic, hence termed “hot" carriers, can exchange energy with the surrounding heat bath, i.e. excite certain phonon modes, which in turn can lead to the breakage of the Si-H passivation bond at the interface and therefore the creation of electrically active amphoteric dangling bond defects, the so called P_b,0-centers. As has been shown by Jech et. al, utilizing ab-initio calculations, this process needs to overcome high energetic barriers and thus can be explained by a resonant phonon mode excitation caused by non-equilibrium energetic carriers [128]. Also, the effect of high energetic non-equilibrium carriers in the interaction with oxide defects at BTI stress conditions has been investigated, resulting in a unified parameter free model for both BTI and HCD (mixed-mode) regimes [127]. The work of Jech et. al emphasized the importance of considering HCD and BTI for an accurate description of the Si/SiO₂ MOSFET degradation over typical device lifetimes.

While the impact of HCD in Si-based MOSFETs on device degradation is undisputed, only little attention has been paid to this effect in SiC MOSFETs. First studies on the effect of HCD stress in SiC MOSFETs revealed changes in the photon emission spectra of the investigated devices [129]. However, it was not possible to extract small relative changes of interface defect densities at already large absolute levels with electrical measurements after HCD stress. With the introduction of more stable NO annealed devices, a significant change of defect densities was observed after HCD stress by performing Charge Pumping (CP) measurements [130]. A clear identification of a defect candidate at the interface such as the P_b,0-center in Si/SiO₂ MOS structures or at the insulator/Si interface of SiON devices [131] was not possible by Electrically Detected Magnetic Resonance (EDMR) measurements [132]. However, an N related defect was suggested to be responsible for the observed increase in the EDMR signal following hot-carrier stress. Determination of the HCD and the role of interface bond breakage in SiC MOSFETs is not as straight forward as in Si-based devices due to the different nature of the interface and a multitude of possible defect configurations and therefore remains unclear to date [133].